Datasheet > MPC96877VK

MPC96877VK

更新时间： 2024-11-11 20:11:19

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		驱动逻辑集成电路
页数	文件大小	规格书
16页	221K
描述
PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PBGA52, 0.65 MM PITCH, LEAD FREE, MAPBGA-52

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

MPC96877VK 技术参数

生命周期：	Transferred	零件包装代码：	BGA
包装说明：	VFBGA, BGA52,6X10,25	针数：	52
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.19	输入调节：	DIFFERENTIAL
JESD-30 代码：	R-PBGA-B52	长度：	7 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	最大I（ol）：	0.009 A
功能数量：	1	反相输出次数：
端子数量：	52	实输出次数：	10
最高工作温度：	70 °C	最低工作温度：
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	VFBGA	封装等效代码：	BGA52,6X10,25
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
电源：	1.8 V	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.04 ns	座面最大高度：	1 mm
子类别：	Clock Drivers	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子形式：	BALL	端子节距：	0.65 mm
端子位置：	BOTTOM	宽度：	4.5 mm
最小 fmax：	340 MHz	Base Number Matches：	1

MPC96877VK 数据手册

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order number: MPC96877

Rev 0, 04/2004

Product Preview

MPC96877

1.8 V PLL 1:10 Differential SDRAM

Clock Driver

DDR II MEMORY

CLOCK / ZERO DELAY BUFFER

Recommended Applications

•

DDR II Memory Modules

Zero Delay Board fan-out

Features

•

1.8-V Phase Lock Loop Clock Driver for (DDR II) Applications

Spread Spectrum Clock Compatible

Operating Frequency: 100 MHz to 340 MHz

1 to 10 differential clock distribution (SSTL_18)

52-Ball VF-BGA (FP-MAPBGA 0.65-mm pitch) and 40-Pin MLF(QFN)

SCALE 2:1

VK SUFFIX

52-BALL FP-MAPBGA PACKAGE

CASE 1544-01

External Feedback Pins (FBIN, FBIN) are used to synchronize the Outputs

to the Input Clocks

•

Single-Ended Input and Single-Ended Output Modes

Meets or Exceeds JESD82-8 PLL Standard for PC2-3200/4300

Auto Power Down detect logic

Switching Characteristics

SCALE 2:1

•

Cycle to Cycle Jitter (>165 Mhz): 40ps max.

Output to Output Skew: 40 ps max.

EP SUFFIX

40-PIN MLF/QFN PACKAGE

CASE 1545-01

Functional Description

The MPC96877 is a high-performance, low-jitter, low-skew, zero-delay buff-

er that distributes a differential clock input pair (CK, CK) to ten differential pairs

of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs

(FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK,

CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS),

and the analog power input (AV_DD). When OE is low, the clock outputs, except

FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its

AVAILABLE ORDERING OPTIONS

T_A

52-Ball BGA

40-Pin QFN

MPC96877VK

(Pb-Free)

MPC96877EP

(Pb-Free)

⁰°C to 70°C

locked-in frequency. OS (output select) is a program pin that must be tied to GND or V_DD. When OS is high, OE functions as previously

described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AV_DDis grounded, the PLL is

turned off and bypassed for test purposes. When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An

input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low

power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being dif-

ferential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback

clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time.

The MPC96877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from 0°C to 70°C.

This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

12 3 4 5 6 7...16

中文翻译

下载PDF

与MPC96877VK相关器件

型号	品牌	获取价格	描述	数据表
MPC96877VKR2	NXP	获取价格	96877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52, 4.5
MPC970	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC970FA	MOTOROLA	获取价格	暂无描述
MPC970FAR2	MOTOROLA	获取价格	250MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP52, TQFP-52
MPC972	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC972FA	IDT	获取价格	Processor Specific Clock Generator, 125MHz, CMOS, PQFP52, LQFP-52
MPC973	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC973FA	NXP	获取价格	973 SERIES, PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLAST
MPC973FA	MOTOROLA	获取价格	PLL Based Clock Driver, 13 True Output(s), 0 Inverted Output(s), PQFP52, LQFP-52
MPC973FAR2	IDT	获取价格	PLL Based Clock Driver, 973 Series, 13 True Output(s), 0 Inverted Output(s), PQFP52, PLAST

与MPC96877VK相关文章

国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

23
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

7
AMD宣布全球裁员约1000人，调整战略聚焦增长
2024-11-14

8
英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

31

产品中心

服务支持

精选活动

关于我们

帮助中心

MPC96877VK

MPC96877VK 技术参数

MPC96877VK 数据手册

与MPC96877VK相关器件

与MPC96877VK相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MPC96877VK

MPC96877VK 技术参数

MPC96877VK 数据手册

与MPC96877VK相关器件

与MPC96877VK相关文章

您还可以找

您在本页遇到什么问题？