Datasheet > MPC96877VK

MPC96877VK

更新时间： 2024-09-23 20:56:59

品牌	Logo	应用领域
艾迪悌 - IDT		驱动逻辑集成电路
页数	文件大小	规格书
13页	442K
描述
PLL Based Clock Driver, 96877 Series, 10 True Output(s), 0 Inverted Output(s), PBGA52, 0.65 MM PITCH, LEAD FREE, MAPBGA-52

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技术参数
数据手册

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MPC96877VK 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	BGA, BGA52,6X10,25	针数：	52
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.19
系列：	96877	输入调节：	DIFFERENTIAL
JESD-30 代码：	R-PBGA-B52	JESD-609代码：	e1
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	最大I（ol）：	0.009 A
湿度敏感等级：	3	功能数量：	1
反相输出次数：		端子数量：	52
实输出次数：	10	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA52,6X10,25
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	260	电源：	1.8 V
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.04 ns
子类别：	Clock Drivers	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	0.635 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	最小 fmax：	340 MHz
Base Number Matches：	1

MPC96877VK 数据手册

Freescale Semiconductor, Inc.

^OrdeD^{r n}A^umT^bA^er:S^MH^PCE⁹⁶E⁸⁷T⁷

Rev 1, 08/2004

TECHNICAL DATA

MPC96877

Product Preview

1.8 V PLL 1:10 Differential SDRAM

Clock Driver

1.8 V PLL 1:10 Differential SDRAM

DDR II MEMORY

CLOCK / ZERO DELAY BUFFER

Recommended Applications

•

DDR II Memory Modules

Zero Delay Board fan-out

Features

•

1.8 V Phase Lock Loop Clock Driver for (DDR II) Applications

Spread Spectrum Clock Compatible

Operating Frequency: 100 MHz to 340 MHz

1 to 10 differential clock distribution (SSTL_18)

52-Ball VF-BGA (FP-MAPBGA 0.65-mm pitch) and 40-Pin MLF (QFN)

52-lead Pb-free Package Available

VK SUFFIX

52-BALL FP-MAPBGA PACKAGE

CASE 1544-01

External Feedback Pins (FBIN, FBIN) are used to synchronize the Outputs

to the Input Clocks

•

Single-Ended Input and Single-Ended Output Modes

Meets or Exceeds JESD82-8 PLL Standard for PC2-3200/4300

Auto Power Down detect logic

EP SUFFIX

40-PIN MLF/QFN PACKAGE

CASE 1545-01

Switching Characteristics

•

Cycle-to-Cycle Jitter (>165 Mhz): 40 ps max.

Output-to-Output Skew: 40 ps max.

AVAILABLE ORDERING OPTIONS

Functional Description

The MPC96877 is a high-performance, low-jitter, low-skew, zero-delay buffer

that distributes a differential clock input pair (CK, CK) to ten differential pairs of

clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs

(FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK,

CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS),

and the analog power input (AV_DD). When OE is low, the clock outputs, except

T_A

52-Ball BGA

40-Pin QFN

MPC96877VK

(Pb-Free)

MPC96877EP

(Pb-Free)

0°C to 70°C

FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin

that must be tied to GND or V_DD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has

no affect on Y7/Y7, they are free running. When AV_DDis grounded, the PLL is turned off and bypassed for test purposes. When both

clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs,

independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the

PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and

the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK,

CK) within the specified stabilization time.

The MPC96877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from 0°C to 70°C.

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

547

MPC96877

IDT™ 1.8 V PLL 1:10 Differential SDRAM Clock Driver

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

12 3 4 5 6 7...13

中文翻译

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与MPC96877VK相关器件

型号	品牌	获取价格	描述	数据表
MPC96877VKR2	NXP	获取价格	96877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52, 4.5
MPC970	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC970FA	MOTOROLA	获取价格	暂无描述
MPC970FAR2	MOTOROLA	获取价格	250MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP52, TQFP-52
MPC972	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC972FA	IDT	获取价格	Processor Specific Clock Generator, 125MHz, CMOS, PQFP52, LQFP-52
MPC973	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC973FA	NXP	获取价格	973 SERIES, PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLAST
MPC973FA	MOTOROLA	获取价格	PLL Based Clock Driver, 13 True Output(s), 0 Inverted Output(s), PQFP52, LQFP-52
MPC973FAR2	IDT	获取价格	PLL Based Clock Driver, 973 Series, 13 True Output(s), 0 Inverted Output(s), PQFP52, PLAST

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