Datasheet > MPC972FA

MPC972FA

更新时间： 2024-09-23 21:22:31

品牌	Logo	应用领域
艾迪悌 - IDT		时钟外围集成电路晶体
页数	文件大小	规格书
13页	631K
描述
Processor Specific Clock Generator, 125MHz, CMOS, PQFP52, LQFP-52

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MPC972FA 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	52
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.34
JESD-30 代码：	S-PQFP-G52	JESD-609代码：	e0
长度：	10 mm	端子数量：	52
最高工作温度：	70 °C	最低工作温度：
最大输出时钟频率：	125 MHz	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	峰值回流温度（摄氏度）：	240
主时钟/晶体标称频率：	100 MHz	认证状态：	Not Qualified
座面最大高度：	1.7 mm	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	20
宽度：	10 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：	1

MPC972FA 数据手册

DATA SHEET

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SEMICONDUCTOR TECHNICAL DATA

Order Number: MPC972/D

Freescale Semiconductor, Inc.

Rev 6, 09/2001

MPC972

Low Voltage PLL Clock Driver

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The MPC972 is a 3.3 V compatible, PLL based clock driver device

targeted for high performance CISC or RISC processor based systems.

With output frequencies of up to 125 MHz and skews of 550 ps the MPC972

is ideally suited for most synchronous systems. The device offers twelve low

skew outputs plus a feedback and sync output for added flexibility and ease

of system implementation.

• Fully Integrated PLL

• Output Frequency up to 125 MHz

• Compatible with PowerPC and Pentium Microprocessors

• LQFP Packaging

LOW VOLTAGE

PLL CLOCK DRIVER

• 3.3 V V_CC

•

100 ps Typical Cycle–to–Cycle Jitter

The MPC972 features an extensive level of frequency programmability

between the 12 outputs as well as the input vs output relationships. Using

the select lines output frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2,

5:3, 6:1 and 6:5 between outputs can be realized by pulsing low one clock

edge prior to the coincident edges of the Qa and Qc outputs. The Sync

output will indicate when the coincident rising edges of the above

relationships will occur. The selectability of the feedback frequency is

independent of the output frequencies, this allows for very flexible

programming of the input reference vs output frequency relationship. The

output frequencies can be either odd or even multiples of the input

reference. In addition the output frequency can be less than the input

frequency for applications where a frequency needs to be reduced by a

non–binary factor. The Power–On Reset ensures proper programming if the

frequency select pins are set at power up. If the fselFB2 pin is held high, it

may be necessary to apply a reset after power–up to ensure

synchronization between the QFB output and the other outputs. The internal

power–on reset is designed to provide this function, but with power–up

conditions being dependent, it is difficult to guarantee. All other conditions of

the fsel pins will automatically synchronize during PLL lock acquisition.

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FA SUFFIX

52–LEAD LQFP PACKAGE

CASE 848D-03

The MPC972 offers a very flexible output enable/disable scheme. This enable/disable scheme helps facilitate system debug as

well as provide unique opportunities for system power down schemes to meet the requirements of “green” class machines. The

MPC972 allows for the enabling of each output independently via a serial input port. When disabled or “frozen” the outputs will be

locked in the “LOW” state, however the internal state machines will continue to run. Therefore when “unfrozen” the outputs will

activate synchronous and in phase with those outputs which were not frozen. The freezing and unfreezing of outputs occurs only

when they are already in the “LOW” state, thus the possibility of runt pulse generation is eliminated. A power-on reset will ensure

that upon power up all of the outputs will be active. Note that all of the control inputs on the MPC972 have internal pull–up resistors.

The MPC972 is fully 3.3 V compatible and requires no external loop filter components. All inputs accept LVCMOS/LVTTL

compatible levels while the outputs provide LVCMOS levels with the capability to drive 50 Ω transmission lines. For series

terminated lines each MPC972 output can drive two 50 Ω lines in parallel thus effectively doubling the fanout of the device.

The MPC972 can consume significant power in some configurations. Users are encouraged to review Application Note

AN1545/D in the Advanced Clock Drivers Device Data book (DL207/D) for a discussion on the thermal issues with the MPC family

of clock drivers.

IDT™ Low Voltage PLL Clock Driver

MPC972

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

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与MPC972FA相关器件

型号	品牌	获取价格	描述	数据表
MPC973	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC973FA	NXP	获取价格	973 SERIES, PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLAST
MPC973FA	MOTOROLA	获取价格	PLL Based Clock Driver, 13 True Output(s), 0 Inverted Output(s), PQFP52, LQFP-52
MPC973FAR2	IDT	获取价格	PLL Based Clock Driver, 973 Series, 13 True Output(s), 0 Inverted Output(s), PQFP52, PLAST
MPC974	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC974FA	NXP	获取价格	974 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLAST
MPC974FA	IDT	获取价格	PLL Based Clock Driver, 974 Series, 14 True Output(s), 0 Inverted Output(s), CMOS, PQFP52,
MPC974FA	MOTOROLA	获取价格	PLL Based Clock Driver, 974 Series, 14 True Output(s), 0 Inverted Output(s), CMOS, PQFP52,
MPC974FAR2	NXP	获取价格	974 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLAST
MPC974FAR2	MOTOROLA	获取价格	974 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, LQFP-

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