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MPC96877VK PDF预览

MPC96877VK

更新时间： 2024-11-12 20:59:43
品牌 Logo 应用领域
恩智浦 - NXP 驱动输出元件逻辑集成电路
页数 文件大小 规格书
16页 226K
描述
96877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52, 4.50 X 7 MM, 0.65 MM PITCH, LEAD FREE, MO-225BA, MAPBGA-52

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MPC96877VK 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：BGA包装说明：VFBGA, BGA52,6X10,25
针数：52Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.19
系列：96877输入调节：DIFFERENTIAL
JESD-30 代码：R-PBGA-B52长度：7 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.009 A
功能数量：1反相输出次数：
端子数量：52实输出次数：10
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装等效代码：BGA52,6X10,25
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
电源：1.8 V认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.04 ns座面最大高度：1 mm
子类别：Clock Drivers最大供电电压 (Vsup)：1.9 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES温度等级：COMMERCIAL
端子形式：BALL端子节距：0.65 mm
端子位置：BOTTOM宽度：4.5 mm
最小 fmax：350 MHzBase Number Matches：1

MPC96877VK 数据手册

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MPC96877  
Rev 1, 11/2004  
Freescale Semiconductor  
Technical Data  
Product Preview  
1.8 V PLL 1:10 Differential SDRAM  
Clock Driver  
MPC96877  
Recommended Applications  
DDR II MEMORY  
CLOCK / ZERO DELAY BUFFER  
•
•
DDR II Memory Modules  
Zero Delay Board fan-out  
Features  
•
•
•
•
•
•
•
1.8 V Phase Lock Loop Clock Driver for (DDR II) Applications  
Spread Spectrum Clock Compatible  
Operating Frequency: 10 MHz to 500 MHz  
1 to 10 differential clock distribution (SSTL_18)  
52-Ball VF-BGA (FP-MAPBGA 0.65-mm pitch) and 40-Pin MLF (QFN)  
52-lead Pb-free Package Available  
VK SUFFIX  
52-BALL FP-MAPBGA PACKAGE  
CASE 1544-01  
External Feedback Pins (FBIN, FBIN) are used to synchronize the Outputs to  
the Input Clocks  
•
•
•
Single-Ended Input and Single-Ended Output Modes  
Meets or Exceeds JESD82-8 PLL Standard for PC2-3200/4300  
Auto Power Down detect logic  
Switching Characteristics  
EP SUFFIX  
40-PIN MLF/QFN PACKAGE  
CASE 1545-01  
•
•
Cycle-to-Cycle Jitter (>165 Mhz): 40 ps max.  
Output-to-Output Skew: 40 ps max.  
Functional Description  
AVAILABLE ORDERING OPTIONS  
The MPC96877 is a high-performance, low-jitter, low-skew, zero-delay buffer  
that distributes a differential clock input pair (CK, CK) to ten differential pairs of  
clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs  
(FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK),  
the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS), and the  
analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/  
FBOUT, are disabled while the internal PLL continues to maintain its locked-in  
TA  
52-Ball BGA  
40-Pin QFN  
0°C to 70°C MPC96877VK MPC96877EP  
(Pb-Free) (Pb-Free)  
frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously  
described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDD is grounded, the PLL  
is turned off and bypassed for test purposes. When both clock inputs (CK, CK) are logic low, the device enters in a low power  
mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and  
performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being  
logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase  
lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time.  
The MPC96877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from 0°C to 70°C.  
This document contains certain information on a new product.  
Specifications and information herein are subject to change without notice.  
© Freescale Semiconductor, Inc., 2004. All rights reserved.  
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