Datasheet > MPC973

MPC973

更新时间： 2024-11-10 22:51:11

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟驱动器
页数	文件大小	规格书
14页	186K
描述
LOW VOLTAGE PLL CLOCK DRIVER

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MPC973 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MPC972/973 are 3.3V compatible, PLL based clock driver

devices targeted for high performance CISC or RISC processor based

systems. With output frequencies of up to 125MHz and skews of 550ps

the MPC972/973 are ideally suited for most synchronous systems. The

devices offer twelve low skew outputs plus a feedback and sync output for

added flexibility and ease of system implementation.

LOW VOLTAGE

PLL CLOCK DRIVER

• Fully Integrated PLL

• Output Frequency up to 125MHz

• Compatible with PowerPC and Pentium Microprocessors

• TQFP Packaging

• 3.3V V

• ± 100ps Typical Cycle–to–Cycle Jitter

The MPC972/973 features an extensive level of frequency

programmability between the 12 outputs as well as the input vs output

relationships. Using the select lines output frequency ratios of 1:1, 2:1,

3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between outputs can be

realized by pulsing low one clock edge prior to the coincident edges of the

Qa and Qc outputs. The Sync output will indicate when the coincident

rising edges of the above relationships will occur. The selectability of the

feedback frequency is independent of the output frequencies, this allows

for very flexible programming of the input reference vs output frequency

relationship. The output frequencies can be either odd or even multiples

of the input reference. In addition the output frequency can be less than

the input frequency for applications where a frequency needs to be

reduced by a non–binary factor. The Power–On Reset ensures proper

programming if the frequency select pins are set at power up. If the

fselFB2 pin is held high, it may be necessary to apply a reset after

power–up to ensure synchronization between the QFB output and the

other outputs. The internal power–on reset is designed to provide this

function, but with power–up conditions being system dependent, it is

difficult to guarantee. All other conditions of the fsel pins will automatically

synchronize during PLL lock acquisition.

FA SUFFIX

52–LEAD TQFP PACKAGE

CASE 848D-03

The MPC972/973 offers a very flexible output enable/disable scheme. This enable/disable scheme helps facilitate system

debug as well as provide unique opportunities for system power down schemes to meet the requirements of “green” class

machines. The MPC972 allows for the enabling of each output independently via a serial input port. When disabled or “frozen”

the outputs will be locked in the “LOW” state, however the internal state machines will continue to run. Therefore when “unfrozen”

the outputs will activate synchronous and in phase with those outputs which were not frozen. The freezing and unfreezing of

outputs occurs only when they are already in the “LOW” state, thus the possibility of runt pulse generation is eliminated. A

power-on reset will ensure that upon power up all of the outputs will be active. Note that all of the control inputs on the

MPC972/973 have internal pull–up resistors.

The MPC972/973 is fully 3.3V compatible and requires no external loop filter components. All inputs accept LVCMOS/LVTTL

compatible levels while the outputs provide LVCMOS levels with the capability to drive 50Ω transmission lines. For series

terminated lines each MPC972/973 output can drive two 50Ω lines in parallel thus effectively doubling the fanout of the device.

The MPC972/973 can consume significant power in some configurations. Users are encouraged to review Application Note

AN1545/D in the Timing Solutions book (BR1333/D) for a discussion on the thermal issues with the MPC family of clock drivers.

PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.

8/97

REV 1

Motorola, Inc. 1997

12 3 4 5 6 7...14

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与MPC973相关器件

型号	品牌	获取价格	描述	数据表
MPC973FA	NXP	获取价格	973 SERIES, PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLAST
MPC973FA	MOTOROLA	获取价格	PLL Based Clock Driver, 13 True Output(s), 0 Inverted Output(s), PQFP52, LQFP-52
MPC973FAR2	IDT	获取价格	PLL Based Clock Driver, 973 Series, 13 True Output(s), 0 Inverted Output(s), PQFP52, PLAST
MPC974	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC974FA	NXP	获取价格	974 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLAST
MPC974FA	IDT	获取价格	PLL Based Clock Driver, 974 Series, 14 True Output(s), 0 Inverted Output(s), CMOS, PQFP52,
MPC974FA	MOTOROLA	获取价格	PLL Based Clock Driver, 974 Series, 14 True Output(s), 0 Inverted Output(s), CMOS, PQFP52,
MPC974FAR2	NXP	获取价格	974 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLAST
MPC974FAR2	MOTOROLA	获取价格	974 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, LQFP-
MPC9772	IDT	获取价格	3.3V 1:12 LVCMOS PLL Clock Generator Internal Power-On Reset

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