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MCM67J518FN9

更新时间： 2024-11-07 22:19:55
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 存储内存集成电路静态存储器输出元件信息通信管理
页数 文件大小 规格书
12页 222K
描述
32K x 18 Bit BurstRAM Synchronous Fast Static RA

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MCM67J518FN9 技术参数

是否Rohs认证：不符合生命周期：Obsolete
包装说明：PLASTIC, LCC-52Reach Compliance Code：unknown
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.92Is Samacsys：N
最长访问时间：9 ns其他特性：OUTPUT REGISTER; SELF-TIMED WRITE; BURST COUNTER; BYTE WRITE
I/O 类型：COMMONJESD-30 代码：S-PQCC-J52
JESD-609代码：e0长度：19.1262 mm
内存密度：589824 bit内存集成电路类型：CACHE SRAM
内存宽度：18功能数量：1
端口数量：1端子数量：52
字数：32768 words字数代码：32000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：32KX18
输出特性：3-STATE可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC52,.8SQ封装形状：SQUARE
封装形式：CHIP CARRIER并行/串行：PARALLEL
电源：5 V认证状态：Not Qualified
座面最大高度：4.57 mm最大待机电流：0.075 A
最小待机电流：4.75 V子类别：SRAMs
最大压摆率：0.275 mA最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD宽度：19.1262 mm
Base Number Matches：1

MCM67J518FN9 数据手册

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Order this document  
by MCM67J518/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM67J518  
32K x 18 Bit BurstRAM  
Synchronous Fast Static RAM  
With Burst Counter and Registered Outputs  
The MCM67J518 is a 589,824 bit synchronous static random access memory  
designed to provide a burstable, high–performance, secondary cache for the  
i486 and Pentium microprocessors. It is organized as 32,768 words of 18  
bits, fabricated withMotorola’s high–performance silicon–gate BiCMOS technol-  
ogy. The device integrates input registers, a 2–bit counter, high speed SRAM,  
and high drive registered output drivers onto a single monolithic circuit for re-  
duced parts count implementation of cache data RAM applications. Synchro-  
nous design allows precise cycle control with the use of an external clock (K).  
BiCMOS circuitry reduces the overall power consumption of the integrated func-  
tions for greater reliability.  
FN PACKAGE  
PLASTIC  
CASE 778–02  
PIN ASSIGNMENT  
Addresses (A0 – A14), data inputs (D0 – D17), and all control signals except  
output enable (G) are clock (K) controlled through positive–edge–triggered  
noninverting registers.  
7
6
5
4
3
2
1 52 51 50 49 48 47  
46  
This device contains output registers for pipeline operations. At the rising edge  
of K, the RAM provides the output data from the previous cycle.  
Output enable (G) is asynchronous for maximum system design flexibility.  
Burst can be initiated with either address status processor (ADSP) or address  
status cache controller (ADSC) input pins. Subsequent burst addresses can be  
generated internally by the MCM67J518 (burst sequence imitates that of the  
i486) and controlled by the burst address advance (ADV) input pin. The following  
pages provide more detailed information on burst controls.  
Write cycles are internally self–timed and are initiated by the rising edge of the  
clock (K) input. This feature eliminates complex off–chip write pulse generation  
and provides increased flexibility for incoming signals.  
Dual write enables (LW and UW) are provided to allow individually writeable  
bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17  
(the upper bits).  
8
9
DQ9  
DQ10  
DQ8  
DQ7  
DQ6  
45  
44  
43  
42  
41  
40  
39  
V
V
10  
CC  
SS  
11  
12  
13  
14  
15  
V
CC  
DQ11  
DQ12  
DQ13  
DQ14  
V
SS  
DQ5  
DQ4  
DQ3  
V
16  
17  
38  
37  
DQ2  
SS  
V
V
CC  
SS  
DQ15  
DQ16  
DQ17  
18  
19  
20  
36  
35  
34  
V
CC  
DQ1  
DQ0  
21 22 23 24 25 26 27 28 29 30 31 32 33  
This device is ideally suited for systems that require wide data bus widths and  
cache memory. See Figure 2 for applications information.  
•
•
Single 5 V ± 5% Power Supply  
Fast Access Time/Fast Cycle Time = 6 ns/100 MHz, 7 ns/80 MHz,  
9 ns/66 MHz  
PIN NAMES  
A0 – A14 . . . . . . . . . . . . . . . . Address Inputs  
K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock  
ADV . . . . . . . . . . . . Burst Address Advance  
LW . . . . . . . . . . . . Lower Byte Write Enable  
UW . . . . . . . . . . . . Upper Byte Write Enable  
ADSC . . . . . . . . . Controller Address Status  
ADSP . . . . . . . . . Processor Address Status  
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable  
G . . . . . . . . . . . . . . . . . . . . . . Output Enable  
DQ0 – DQ17 . . . . . . . . . . Data Input/Output  
•
•
•
•
•
•
•
•
•
•
Byte Writeable via Dual Write Enables  
Internal Input Registers (Address, Data, Control)  
Output Registers for Pipelined Applications  
Internally Self–Timed Write Cycle  
ADSP, ADSC, and ADV Burst Control Pins  
Asynchronous Output Enable Controlled Three–State Outputs  
Common Data Inputs and Data Outputs  
3.3 V I/O Compatible  
V
CC  
V
SS  
. . . . . . . . . . . . . . . . + 5 V Power Supply  
. . . . . . . . . . . . . . . . . . . . . . . . . . Ground  
NC . . . . . . . . . . . . . . . . . . . . . No Connection  
High Board Density 52–Lead PLCC Package  
ADSP Disabled with Chip Enable (E) – Supports Address Pipelining  
All power supply and ground pins must be  
connected for proper operation of the device.  
BurstRAM is a trademark of Motorola, Inc.  
i486 and Pentium are trademarks of Intel Corp.  
REV 3  
5/95  
Motorola, Inc. 1994  
1234567...12

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