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MCM67J618AFN7 PDF预览

MCM67J618AFN7

更新时间： 2024-11-25 14:34:31
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 信息通信管理静态存储器输出元件内存集成电路
页数 文件大小 规格书
12页 216K
描述
Cache SRAM, 64KX18, 7ns, BICMOS, PQCC52, PLASTIC, LCC-52

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中文翻译

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MCM67J618AFN7 技术参数

生命周期：Obsolete零件包装代码：LCC
包装说明：QCCJ, LDCC52,.8SQ针数：52
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.84
Is Samacsys：N最长访问时间：7 ns
其他特性：OUTPUT REGISTER; SELF-TIMED WRITE; BURST COUNTER; BYTE WRITEI/O 类型：COMMON
JESD-30 代码：S-PQCC-J52JESD-609代码：e0
长度：19.1262 mm内存密度：1179648 bit
内存集成电路类型：CACHE SRAM内存宽度：18
功能数量：1端口数量：1
端子数量：52字数：65536 words
字数代码：64000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：64KX18输出特性：3-STATE
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC52,.8SQ
封装形状：SQUARE封装形式：CHIP CARRIER
并行/串行：PARALLEL电源：5 V
认证状态：Not Qualified座面最大高度：4.57 mm
最大待机电流：0.075 A最小待机电流：4.75 V
子类别：SRAMs最大压摆率：0.29 mA
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BICMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
宽度：19.1262 mmBase Number Matches：1

MCM67J618AFN7 数据手册

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Order this document  
by MCM67J618A/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM67J618A  
Product Preview  
64K x 18 Bit BurstRAM  
Synchronous Fast Static RAM  
With Burst Counter and Registered Outputs  
The MCM67J618A is a 1,179,648 bit synchronous static random access  
memory designed to provide a burstable, high–performance, secondary cache  
for the i486 and Pentium microprocessors. It is organized as 65,536 words  
of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS  
technology. The device integrates input registers, a 2–bit counter, high speed  
SRAM, and high drive registered output drivers onto a single monolithic circuit  
for reduced parts count implementation of cache data RAM applications. Syn-  
chronousdesignallowsprecisecyclecontrolwiththeuseofanexternalclock(K).  
BiCMOS circuitry reduces the overall power consumption of the integrated func-  
tions for greater reliability.  
FN PACKAGE  
PLASTIC  
CASE 778–02  
PIN ASSIGNMENT  
7
6
5
4
3
2
1 52 51 50 49 48 47  
46  
Addresses (A0 – A15), data inputs (D0 – D17), and all control signals except  
output enable (G) are clock (K) controlled through positive–edge–triggered non-  
inverting registers.  
8
9
DQ9  
DQ10  
DQ8  
DQ7  
DQ6  
45  
44  
43  
42  
41  
40  
39  
V
V
10  
CC  
SS  
This device contains output registers for pipeline operations. At the rising edge  
of K, the RAM provides the output data from the previous cycle.  
Output enable (G) is asynchronous for maximum system design flexibility.  
Burst can be initiated with either address status processor (ADSP) or address  
status cache controller (ADSC) input pins. Subsequent burst addresses can be  
generated internally by the MCM67J618A (burst sequence imitates that of the  
i486) and controlled by the burst address advance (ADV) input pin. The following  
pages provide more detailed information on burst controls.  
11  
12  
13  
14  
15  
V
CC  
DQ11  
DQ12  
DQ13  
DQ14  
V
SS  
DQ5  
DQ4  
DQ3  
V
16  
17  
38  
37  
DQ2  
SS  
V
V
CC  
SS  
DQ15  
DQ16  
DQ17  
18  
19  
20  
36  
35  
34  
V
CC  
Write cycles are internally self–timed and are initiated by the rising edge of the  
clock (K) input. This feature eliminates complex off–chip write pulse generation  
and provides increased flexibility for incoming signals.  
DQ1  
DQ0  
21 22 23 24 25 26 27 28 29 30 31 32 33  
Dual write enables (LW and UW) are provided to allow individually writeable  
bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17  
(the upper bits).  
This device is ideally suited for systems that require wide data bus widths and  
cache memory. See Figure 2 for applications information.  
PIN NAMES  
A0 – A15 . . . . . . . . . . . . . . . . Address Inputs  
K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock  
ADV . . . . . . . . . . . . Burst Address Advance  
LW . . . . . . . . . . . . Lower Byte Write Enable  
UW . . . . . . . . . . . . Upper Byte Write Enable  
ADSC . . . . . . . . . Controller Address Status  
ADSP . . . . . . . . . Processor Address Status  
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable  
G . . . . . . . . . . . . . . . . . . . . . . Output Enable  
DQ0 – DQ17 . . . . . . . . . . Data Input/Output  
•
•
•
•
•
•
•
•
•
•
•
•
Single 5 V ± 5% Power Supply  
Fast Access Time/Fast Cycle Time = 5 ns/100 MHz, 7 ns/80 MHz  
Byte Writeable via Dual Write Enables  
Internal Input Registers (Address, Data, Control)  
Output Registers for Pipelined Applications  
Internally Self–Timed Write Cycle  
ADSP, ADSC, and ADV Burst Control Pins  
Asynchronous Output Enable Controlled Three–State Outputs  
Common Data Inputs and Data Outputs  
3.3 V I/O Compatible  
High Board Density 52–Lead PLCC Package  
ADSP Disabled with Chip Enable (E) – Supports Address Pipelining  
V
CC  
V
SS  
. . . . . . . . . . . . . . . . + 5 V Power Supply  
. . . . . . . . . . . . . . . . . . . . . . . . . . Ground  
All power supply and ground pins must be  
connected for proper operation of the device.  
BurstRAM is a trademark of Motorola, Inc.  
i486 and Pentium are trademarks of Intel Corp.  
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.  
REV 1  
5/95  
Motorola, Inc. 1995  
1234567...12

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