MCM67M618BFN12R

更新时间： 2024-09-19 13:11:23

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		存储内存集成电路静态存储器信息通信管理
页数	文件大小	规格书
12页	170K
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MCM67M618BFN12R 数据手册

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SEMICONDUCTOR TECHNICAL DATA

MCM67M618B

Advance Information

64K x 18 Bit BurstRAM

Synchronous Fast Static RAM

With Burst Counter and Self–Timed Write

The MCM67M618B is a 1,179,648 bit synchronous static random access

memory designed to provide a burstable, high–performance, secondary cache

for the MC68040 and PowerPC microprocessors. It is organized as 65,536

words of 18 bits, fabricated using Motorola’s high–performance silicon–gate

BiCMOS technology. The device integrates input registers, a 2–bit counter, high

speed SRAM, and high drive capability outputs onto a single monolithic circuit

for reduced parts count implementation of cache data RAM applications. Syn-

chronous design allows precise cycle control with the use of an external clock

(K). BiCMOS circuitry reduces the overall power consumption of the integrated

functions for greater reliability.

FN PACKAGE

PLASTIC

CASE 778–02

PIN ASSIGNMENT

1 52 51 50 49 48 47

46 DQ8

Addresses (A0 – A15), data inputs (DQ0 – DQ17), and all control sig-

nals, except output enable (G), are clock (K) controlled through posi-

tive–edge–triggered noninverting registers.

DQ9

DQ10

45 DQ7

44 DQ6

Bursts can be initiated with either transfer start processor (TSP) or

transfer start cache controller (TSC) input pins. Subsequent burst

addresses are generated internally by the MCM67M618B (burst

sequence imitates that of the MC68040) and controlled by the burst

address advance (BAA) input pin. The following pages provide more

detailed information on burst controls.

Write cycles are internally self–timed and are initiated by the rising

edge of the clock (K) input. This feature eliminates complex off–chip

write pulse generation and provides increased flexibility for incoming

signals.

DQ11

DQ12

DQ13

DQ14

41 DQ5

40 DQ4

39 DQ3

DQ15

DQ16

DQ17

38 DQ2

35 DQ1

34 DQ0

21 22 23 24 25 26 27 28 29 30 31 32 33

Dual write enables (LW and UW) are provided to allow individually

writeable bytes. LW controls DQ0 – DQ8 (the lower bits), while UW

controls DQ9 – DQ17 (the upper bits).

This device is ideally suited for systems that require wide data bus

widths and cache memory.

PIN NAMES

A0 – A15 . . . . . . . . . . . . . . . . Address Inputs

K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock

BAA . . . . . . . . . . . . Burst Address Advance

LW . . . . . . . . . . . . Lower Byte Write Enable

UW . . . . . . . . . . . . Upper Byte Write Enable

TSP, TSC . . . . . . . . . . . . . . . . Transfer Start

E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable

G . . . . . . . . . . . . . . . . . . . . . . Output Enable

DQ0 – DQ17 . . . . . . . . . . Data Input/Output

•

Single 5 V ± 5% Power Supply

Fast Access Times: 9/10/12 ns Max

Byte Writeable via Dual Write Strobes

Internal Input Registers (Address, Data, Control)

Internally Self–Timed Write Cycle

TSP, TSC, and BAA Burst Control Pins

Asynchronous Output Enable Controlled Three–State Outputs

Common Data Inputs and Data Outputs

High Board Density 52–PLCC Package

3.3 V I/O Compatible

. . . . . . . . . . . . . . . . + 5 V Power Supply

. . . . . . . . . . . . . . . . . . . . . . . . . . Ground

All power supply and ground pins must be con-

nected for proper operation of the device.

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

REV 1

7/15/97

Motorola, Inc. 1997

MOTOROLA FAST SRAM

MCM67M618B

12 3 4 5 6 7...12

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与MCM67M618BFN12R相关器件

型号	品牌	获取价格	描述	数据表
MCM67M618BFN9	MOTOROLA	获取价格	64K x 18 Bit BurstRAM Synchronous Fast Static RAM
MCM67M618FN11	MOTOROLA	获取价格	Cache SRAM, 64KX18, 11ns, BICMOS, PQCC52, PLASTIC, LCC-52
MCM67N518AFN5	MOTOROLA	获取价格	32KX18 CACHE SRAM, 5ns, PQCC52, PLASTIC, LCC-52
MCM67N518AFN7	MOTOROLA	获取价格	32KX18 CACHE SRAM, 7ns, PQCC52, PLASTIC, LCC-52
MCM67N618AFN5	MOTOROLA	获取价格	64KX18 CACHE SRAM, PQCC52, PLASTIC, LCC-52
MCM67N618AFN7	MOTOROLA	获取价格	64KX18 CACHE SRAM, PQCC52, PLASTIC, LCC-52
MCM67P618FN6	MOTOROLA	获取价格	64KX18 APPLICATION SPECIFIC SRAM, 6ns, PQCC52, PLASTIC, LCC-52
MCM67P618FN8	MOTOROLA	获取价格	64KX18 APPLICATION SPECIFIC SRAM, 8ns, PQCC52, PLASTIC, LCC-52
MCM67P804WJ10	MOTOROLA	获取价格	256KX4 APPLICATION SPECIFIC SRAM, 6ns, PDSO32, 0.400 INCH, SOJ-32
MCM67P804WJ10R2	MOTOROLA	获取价格	256KX4 APPLICATION SPECIFIC SRAM, 6ns, PDSO32, 0.400 INCH, SOJ-32

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