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MCM67Q909

更新时间： 2024-11-07 22:19:55
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
10页 143K
描述
512K x 9 Bit Separate I/O Synchronous Fast Static RAM

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MCM67Q909 数据手册

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Order this document  
by MCM67Q909/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM67Q909  
Advance Information  
512K x 9 Bit Separate I/O  
Synchronous Fast Static RAM  
The MCM67Q909 is a 4M–bit static random access memory, organized as  
512K words of 9 bits. It features separate TTL input and output buffers, which  
drive 3.3 V output levels, and incorporates input and output registers on–board  
withhighspeedSRAM. Italsofeaturestransparent–writeanddatapass–through  
capabilities.  
86 BUMP PBGA  
CASE 896A–02  
The synchronous design allows for precise cycle control with the use of an  
external single clock (K). The addresses (A0 – A18), data input (D0 – D8), data  
output (Q0 – Q8), write–enable (W), chip–enable (E), andoutput–enable(G), are  
registered on the rising edge of clock (K).  
The control pins (E, W, G) function differently in comparison to most synchro-  
nous SRAMs. This device will not deselect with E high. The RAM remains active  
at all times. If E is registered high, the output pins (Q0 – Q8) will be driven if G  
is registered low. The transparent write feature allows the output data to track the  
input data. E, G, and W must be asserted to perform a transparent write (write  
and pass–through). The input data is available at the ouputs on the next rising  
edge of clock (K).  
The pass–through function is always enabled. E high disables the write to the  
array while allowing a pass–through cycle to occur on the next rising edge of  
clock (K). Only a registered G high will three–state the outputs.  
The MCM67Q909 is available in an 86–bump surface mount PBGA (Plastic  
Ball Grid Array) package.  
PIN NAMES  
A0 – A18 . . . . . . . . . . . . . . . . . Address Input  
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable  
W . . . . . . . . . . . . . . . . . . . . . . . . Write Enable  
G . . . . . . . . . . . . . . . . . . . . . . Output Enable  
D0 – D8 . . . . . . . . . . . . . . . . . . . . Data Inputs  
Q0 – Q8 . . . . . . . . . . . . . . . . . . Data Outputs  
K . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input  
SCK . . . . . . . . . . . . . . . . . . Scan Clock Input  
SE . . . . . . . . . . . . . . . . . . . . . . . Scan Enable  
SDI . . . . . . . . . . . . . . . . . . . . Scan Data Input  
SDO . . . . . . . . . . . . . . . . . Scan Data Output  
V
CC  
V
SS  
. . . . . . . . . . . . . . . + 5 V Power Supply  
. . . . . . . . . . . . . . . . . . . . . . . . . . Ground  
NC . . . . . . . . . . . . . . . . . . . . . No Connection  
•
•
•
•
•
•
•
•
•
•
•
•
Single 5 V ± 5% Power Supply  
Fast Cycle Time: 12 ns Max  
Single Clock Operation  
PIN ASSIGNMENT  
4
5
6
7
8
9
1
2
3
TTL Input and Output Levels (Outputs LVTTL Compatible)  
Address, Data Input, E, W, and G Registers On–Chip  
83 MHz Maximum Clock Cycle Time  
Self–Timed Write  
Separate Data Input and Output Pins  
Transparent–Write and Pass–Through  
High Output Drive Capability: 50 pF/Output at Rated Access Time  
Boundary Scan Implementation  
A
B
E
W
G
V
SDI SDO A4  
A6 A2  
A0  
CC  
A16 A14  
D7  
K
V
V
D8  
SS  
SS  
C
D
E
F
A15 A17  
Q7  
V
V
V
V
Q8  
Q6  
V
SS  
SS  
SS  
SS  
SS  
V
V
V
V
V
V
V
D6  
SS  
SS  
SS SS  
SS  
SS  
D5  
V
V
V
V
V
V
V
V
CC  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
PBGA Package for High Speed Operation  
V
Q5  
V
V
V
V
D4 Q4  
CC  
SS  
SS  
SS  
SS SS  
SS  
SS  
SS  
G
D3  
Q3  
D1  
V
V
V
V
SS  
V
V
D2  
D0  
Q2  
SS  
SS  
H
V
A18  
V
V
V
V
SS  
SS  
SS SS  
SS  
J
Q1 A12 A10  
V
A9  
A8  
SE  
A5  
A7  
A1  
A3  
Q0  
SS  
K
A13 A11 SCK  
V
CC  
TOP VIEW  
86–BUMP  
Not to Scale  
This document contains information on a new product. Specifications and information herein are subject to change without notice.  
REV 3  
12/23/97  
Motorola, Inc. 1997  
1234567...10

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