Datasheet > MCM67T415

MCM67T415

更新时间： 2024-09-18 22:19:59

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		/
页数	文件大小	规格书
3页	102K
描述
16K x 15 Bit Cache Tag RAM for Pentium Processors

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技术参数
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MCM67T415 技术参数

生命周期：	Obsolete	包装说明：	TQFP-80
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.41	风险等级：	5.84
JESD-30 代码：	S-PQFP-G80	长度：	14 mm
内存密度：	245760 bit	内存集成电路类型：	CACHE TAG SRAM
内存宽度：	15	功能数量：	1
端子数量：	80	字数：	16384 words
字数代码：	16000	工作模式：	SYNCHRONOUS
组织：	16KX15	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装形状：	SQUARE
封装形式：	FLATPACK	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	1.74 mm
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	BICMOS	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
宽度：	14 mm	Base Number Matches：	1

MCM67T415 数据手册

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by MCM67T415/D

SEMICONDUCTOR TECHNICAL DATA

MCM67T415

Advance Information

16K x 15 Bit Cache Tag RAM

for Pentium Processors

The MCM67T415 is a 245,760 bit cache–tag static RAM designed to support

Pentium microprocessors at bus speeds up to 66 MHz. It is organized as 16K words

of 15 bits each and is fabricated using Motorola‘s high performance, silicon gate

BiCMOS technology. There are twelve common I/O tag bits and three separate I/O

status bits. A 12–bit comparator is on–chip to allow fast comparison of the 12 stored

tag bits with the current tag input data. An active high MATCH output is generated

when the valid bit is true and these two groups of data are the same for a given

address.

TQ PACKAGE

TQFP

CASE 917A–02

This high–speed MATCH signal, with t

fastest possible enabling of secondary cache accesses.

times as fast as 9 ns, provides the

AVMV

The three separate I/O status bits (VALID, DIRTY, and WT) can be configured for

either dedicated or generic functionality, depending on the SFUNC input pin. With

SFUNC low, the status bits are defined and used internally by the device, allowing

easier determination of the validity and use of the given tag data. SFUNC high

releases the defined internal status bit usage and control, allowing users to

configure the status bit information to fit their system needs. A synchronous RESET

pin, when held low at a rising clock edge, will reset all status bits in the array for easy

invalidation of all tag addresses.

The MCM67T415 also provides the option for burst ready (BRDY) generation

withinthecachetagitself, baseduponMATCH, VALIDbit, WTbit, andotherexternal

inputs provided by the user. This can significantly simplify cache controller logic and

minimize cache decision time. Match and read operations are both asynchronous

in order to provide the fastest access times possible, while write operations are

synchronous for ease of system timing.

TheMCM67T415usesa5VpowersupplyonV

andV ,withseparateV

CCQ

pins provided for the outputs to offer compliance with both 5 V TTL and 3.3 V LVTTL

logic levels. The PWRDN pin offers a low–power standby mode, which provides

significant system power savings.

The MCM67T415 is offered in a space saving 80–pin thin quad flat pack (TQFP)

package.

•

16K x 15 Configuration:

– 12 Tag Bits

– Three Status Bits (Valid, Dirty, and WT)

Valid Bit used to Qualify Match Output

High–Speed Address–to–Match Comparison Times – 9/10/12 ns

BRDY Circuitry Included Inside the Cache–Tag for the Highest Speed

Operation

•

Asynchronous Read/Match Operation and Synchronous Write and Reset

Operation

•

Separate Write Enable for Tag Bits and Status Bits

Separate Output Enable for Tag Bits, Status Bits, and BRDY

Synchronous RESET Pin for Invalidation of all Tag Entries

Dual Chip Selects for Easy Depth Expansion with No Performance

Degradation

•

I/O Pins Both 5 V TTL and 3.3 V LVTTL Compatible with V

PWRDN Pin to Place Device in Low–Power Mode

Drop–In Replacement for IDT71215

Pins

CCQ

Packaged in an 80–Pin Thin Quad Flat Pack (TQFP)

Pentium is a trademark of Intel Corp.

This document contains information on a new product. Motorola reserves the right to change or discontinue this product without notice.

9/10/96

Motorola, Inc. 1996

MOTOROLA FAST SRAM

MCM67T415

12 3

中文翻译

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与MCM67T415相关器件

型号	品牌	获取价格	描述	数据表
MCM67T415TQ	MOTOROLA	获取价格	16K x 15 Bit Cache Tag RAM for Pentium Processors
MCM67W518FN12	MOTOROLA	获取价格	32K X 18 CACHE TAG SRAM, 12 ns, PQCC52, PLASTIC, LCC-52
MCM67W518FN15	MOTOROLA	获取价格	32K X 18 CACHE TAG SRAM, 15 ns, PQCC52, PLASTIC, LCC-52
MCM67W518FN20	MOTOROLA	获取价格	32KX18 CACHE TAG SRAM, 20ns, PQCC52, PLASTIC, LCC-52
MCM67W618FN12	MOTOROLA	获取价格	64KX18 CACHE TAG SRAM, 12ns, PQCC52, PLASTIC, LCC-52
MCM67W618FN20	MOTOROLA	获取价格	64KX18 CACHE TAG SRAM, 20ns, PQCC52, PLASTIC, LCC-52
MCM6810	MOTOROLA	获取价格	128 8-bit Random-Access Memory
MCM6810	FREESCALE	获取价格	8-BIT MPUS, 8-BIT MCUS, 8-BIT PERIPHERALS
MCM6810ACL	MOTOROLA	获取价格	Standard SRAM, 128X8, MOS, CDIP24
MCM6810AL	MOTOROLA	获取价格	Standard SRAM, 128X8, MOS, CDIP24

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