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MCM67M618AFN12R PDF预览

MCM67M618AFN12R

更新时间： 2024-11-21 13:01:51
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 存储内存集成电路静态存储器信息通信管理
页数 文件大小 规格书
12页 209K
描述
Cache SRAM, 64KX18, 12ns, BICMOS, PQCC52, PLASTIC, LCC-52

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MCM67M618AFN12R 技术参数

生命周期：Obsolete包装说明：QCCJ,
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.79
最长访问时间：12 ns其他特性：SELF-TIMED WRITE; BURST COUNTER; BYTE WRITE
JESD-30 代码：S-PQCC-J52长度：19.1262 mm
内存密度：1179648 bit内存集成电路类型：CACHE SRAM
内存宽度：18功能数量：1
端口数量：1端子数量：52
字数：65536 words字数代码：64000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：64KX18
输出特性：3-STATE可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装形状：SQUARE封装形式：CHIP CARRIER
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：4.57 mm最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：COMMERCIAL端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
宽度：19.1262 mmBase Number Matches：1

MCM67M618AFN12R 数据手册

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Order this document  
by MCM67M618A/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM67M618A  
Product Preview  
64K x 18 Bit BurstRAM  
Synchronous Fast Static RAM  
With Burst Counter and Self–Timed Write  
The MCM67M618A is a 1,179,648 bit synchronous static random access  
memory designed to provide a burstable, high–performance, secondary cache  
for the MC68040 and PowerPC microprocessors. It is organized as 65,536  
words of 18 bits, fabricated using Motorola’s high–performance silicon–gate  
BiCMOS technology. The device integrates input registers, a 2–bit counter, high  
speed SRAM, and high drive capability outputs onto a single monolithic circuit  
for reduced parts count implementation of cache data RAM applications. Syn-  
chronousdesignallowsprecisecyclecontrolwiththeuseofanexternalclock(K).  
BiCMOS circuitry reduces the overall power consumption of the integrated func-  
tions for greater reliability.  
FN PACKAGE  
PLASTIC  
CASE 778–02  
PIN ASSIGNMENT  
7
6
5
4
3
2
1 52 51 50 49 48 47  
46  
8
9
Addresses (A0 – A15), data inputs (DQ0 – DQ17), and all control signals,  
except output enable (G), are clock (K) controlled through positive–edge–  
triggered noninverting registers.  
DQ9  
DQ10  
DQ8  
DQ7  
DQ6  
45  
44  
43  
42  
41  
V
V
10  
CC  
SS  
11  
12  
13  
14  
15  
V
Bursts can be initiated with either transfer start processor (TSP) or transfer  
start cache controller (TSC) input pins. Subsequent burst addresses are gen-  
erated internally by the MCM67M618A (burst sequence imitates that of the  
MC68040) and controlled by the burst address advance (BAA) input pin. The  
following pages provide more detailed information on burst controls.  
Write cycles are internally self–timed and are initiated by the rising edge of the  
clock (K) input. This feature eliminates complex off–chip write pulse generation  
and provides increased flexibility for incoming signals.  
CC  
DQ11  
DQ12  
DQ13  
DQ14  
V
DQ5  
SS  
40 DQ4  
39 DQ3  
38 DQ2  
V
16  
17  
SS  
V
37  
V
V
CC  
SS  
CC  
DQ15  
DQ16  
DQ17  
18  
19  
20  
36  
35 DQ1  
34 DQ0  
Dual write enables (LW and UW) are provided to allow individually writeable  
bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17  
(the upper bits).  
21 22 23 24 25 26 27 28 29 30 31 32 33  
This device is ideally suited for systems that require wide data bus widths and  
cache memory.  
PIN NAMES  
•
•
•
•
•
•
•
•
•
•
Single 5 V ± 5% Power Supply  
Fast Access Times: 9/10/12 ns Max  
Byte Writeable via Dual Write Strobes  
Internal Input Registers (Address, Data, Control)  
Internally Self–Timed Write Cycle  
TSP, TSC, and BAA Burst Control Pins  
Asynchronous Output Enable Controlled Three–State Outputs  
Common Data Inputs and Data Outputs  
High Board Density 52–PLCC Package  
3.3 V I/O Compatible  
A0 – A15 . . . . . . . . . . . . . . . . Address Inputs  
K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock  
BAA . . . . . . . . . . . . Burst Address Advance  
LW . . . . . . . . . . . . Lower Byte Write Enable  
UW . . . . . . . . . . . . Upper Byte Write Enable  
TSP, TSC . . . . . . . . . . . . . . . . Transfer Start  
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable  
G . . . . . . . . . . . . . . . . . . . . . . Output Enable  
DQ0 – DQ17 . . . . . . . . . . Data Input/Output  
V
CC  
V
SS  
. . . . . . . . . . . . . . . . + 5 V Power Supply  
. . . . . . . . . . . . . . . . . . . . . . . . . . Ground  
All power supply and ground pins must be  
connected for proper operation of the device.  
BurstRAM is a trademark of Motorola, Inc.  
PowerPC is a trademark of IBM Corp.  
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.  
REV 1  
5/95  
Motorola, Inc. 1994  
1234567...12

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