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MC100LVEL90 PDF预览

MC100LVEL90

更新时间: 2024-11-26 22:58:07
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
4页 118K
描述
Triple ECL to PECL Translator

MC100LVEL90 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC100LVEL/EL90 is a triple ECL to PECL translator. The device  
receives either standard or low voltage differential ECL signals and  
translates them to either standard or low voltage differential PECL output  
signals. The LVEL device can handle the low voltage signals while the EL  
device is designed for the standard signals. It is possible to have low  
voltage signals on one side and standard signals on the other if the  
LVEL90 is used.  
500ps Propagation Delays  
Fully Differential Design  
20  
Supports both Standard and Low Voltage Operation  
20–Lead SOIC Packaging  
1
A V  
BB  
output is provided for interfacing with single ended ECL signals  
output should be  
at the input. If a single ended input is to be used the V  
BB  
DW SUFFIX  
PLASTIC SOIC PACKAGE  
CASE 751D-04  
connected to the D input. The active signal would then drive the D input.  
When used the V output should be bypassed to ground via a 0.01µF  
capacitor. The V  
for the EL90 under single ended input switching conditions, as a result  
this pin can only source/sink up to 0.5mA of current.  
BB  
output is designed to act as the switching reference  
BB  
To accomplish the level translation the EL/LVEL90 requires three  
power rails. The V  
and the V  
EE  
supply should be connected to the positive supply,  
pin should be connected to the negative power supply. The  
CC  
GND pins as expected are connected to the system ground plain. Both  
and V should be bypassed to ground via 0.01µF capacitors.  
V
EE  
CC  
Under open input conditions, the D input will be biased at V /2 and  
the D input will be pulled to V . This condition will force the Q output to a  
EE  
LOW, ensuring stability.  
EE  
PIN NAMES  
Pins  
Function  
Dn  
Qn  
ECL Inputs  
PECL Outputs  
V
BB  
ECL Reference Voltage Output  
Logic Diagram and Pinout: 20-Lead SOIC (Top View)  
V
Q0  
19  
Q0  
18  
GND  
17  
Q1  
16  
Q1  
15  
GND  
14  
Q2  
13  
Q2  
12  
V
CC  
CC  
20  
11  
PECL  
PECL  
PECL  
ECL  
ECL  
ECL  
1
2
3
4
5
6
7
8
9
10  
V
D0  
D0  
V
D1  
D1  
V
D2  
D2  
V
EE  
CC  
BB  
BB  
7/95  
Motorola, Inc. 1996  
REV 1  

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