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MC100LVEL91 PDF预览

MC100LVEL91

更新时间: 2024-02-16 03:26:08
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
4页 84K
描述
Triple PECL to ECL Translator

MC100LVEL91 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC100LVEL/EL91 is a triple PECL to ECL translator. The  
MC100LVEL91 receives low voltage PECL signals and translates them to  
differential ECL output signals. The MC100EL91 receives standard  
voltage PECL signals and translates them to differential ECL output  
signals.  
MC100LVEL91 Supports Low Voltage Operation  
MC100LVEL91 Has 620ps Typical Propagation Delays  
MC100EL91 Supports Standard Voltage Operation  
MC100EL91 Has 670ps Typical Propagation Delays  
Fully Differential Design  
20–lead SOIC Packaging  
DW SUFFIX  
20–LEAD PLASTIC SOIC WIDE PACKAGE  
CASE 751D–04  
A V  
BB  
output is provided for interfacing with single ended PECL signals  
output should be  
at the input. If a single ended input is to be used the V  
BB  
connected to the D input. The active signal would then drive the D input.  
When used the V output should be bypassed to ground via a 0.01µF  
capacitor. The V  
for the EL/LVEL91 under single ended input switching conditions, as a  
result this pin can only source/sink up to 0.5mA of current.  
BB  
output is designed to act as the switching reference  
BB  
To accomplish the level translation the EL/LVEL91 requires three  
power rails. The V  
supply should be connected to the positive supply,  
pin should be connected to the negative power supply. The  
CC  
and the V  
EE  
PIN NAMES  
GND pins are connected to the system ground plain. Both V  
and V  
EE  
CC  
Pins  
Function  
should be bypassed to ground via 0.01µF capacitors.  
Under open input conditions, the D input will be biased at V /2 and  
CC  
the D input will be pulled to GND. This condition will force the Q output to  
a low, ensuring stability.  
Dn  
Qn  
PECL_V  
PECL/LVPECL Inputs  
ECL/LVECL Outputs  
PECL Reference Voltage Output  
BB  
V
Q0  
19  
Q0  
18  
GND  
17  
Q1  
16  
Q1  
15  
GND  
14  
Q2  
13  
Q2  
12  
V
CC  
CC  
20  
11  
ECL  
ECL  
ECL  
PECL  
1
PECL  
PECL  
7
2
3
4
5
6
8
9
10  
V
D0  
D0  
D1  
D1  
D2  
D2  
V
EE  
CC  
Figure 1. 20–Lead Pinout (Top View) and Logic Diagram  
8/97  
Motorola, Inc. 1997  
REV 1  

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