Datasheet > MC100LVEL91_06

MC100LVEL91_06

更新时间： 2024-01-05 18:08:05

品牌	Logo	应用领域
安森美 - ONSEMI		转换器
页数	文件大小	规格书
6页	112K
描述
3.3 V Triple LVPECL Input to −3.3 V to −5.0 V ECL Output Translator

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MC100LVEL91_06 数据手册

MC100LVEL91

3.3 V Triple LVPECL Input to

−3.3 V to −5.0 V ECL Output

Translator

Description

http://onsemi.com

The MC100LVEL91 is a triple LVPECL input to ECL output

translator. The device receives low voltage differential PECL signals,

MARKING

DIAGRAM*

determined by the V supply level, and translates them to differential

−3.3 V to −5.0 V ECL output signals.

To accomplish the level translation the LVEL91 requires three

power rails. The V

supply should be connected to the positive

supply, and the V pin should be connected to the negative power

supply. The GND pins are connected to the system ground plane. Both

MC100LVEL91

AWLYYWWG

and V should be bypassed to ground via 0.01 mF capacitors.

Under open input conditions, the D input will be biased at V /2

SO−20

and the D input will be pulled to GND. This condition will force the

Q output to a low, ensuring stability.

DW SUFFIX

CASE 751D

The V pin, an internally generated voltage supply, is available to

this device only. For single-ended input conditions, the unused

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

differential input is connected to V as a switching reference voltage.

may also rebias AC coupled inputs. When used, decouple V

and V via a 0.01 mF capacitor and limit current sourcing or sinking

to 0.5 mA. When not used, V should be left open.

*For additional marking information, refer to

Application Note AND8002/D.

Features

• 620 ps Typical Propagation Delay

• The 100 Series Contains Temperature Compensation

• Operating Range: V = 3.8 V to 3.0 V;

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

= −3.0 V to −5.5 V; GND = 0 V

• Q Output will Default LOW with Inputs Open or at GND

• Pb−Free Packages are Available*

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

November, 2006 − Rev. 10

MC100LVEL91/D

12 3 4 5 6

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与MC100LVEL91_06相关器件

型号	品牌	获取价格	描述	数据表
MC100LVEL91DW	ONSEMI	获取价格	3.3 V Triple LVPECL Input to −3.3 V to −5.0 V ECL Output Translator
MC100LVEL91DW	MOTOROLA	获取价格	Triple PECL to ECL T ranslator
MC100LVEL91DWG	ONSEMI	获取价格	3.3 V Triple LVPECL Input to −3.3 V to −5.0 V ECL Output Translator
MC100LVEL91DWR2	ONSEMI	获取价格	3.3 V Triple LVPECL Input to −3.3 V to −5.0 V ECL Output Translator
MC100LVEL91DWR2G	ONSEMI	获取价格	3.3 V Triple LVPECL Input to −3.3 V to −5.0 V ECL Output Translator
MC100LVEL92	ONSEMI	获取价格	Triple PECL to LVPECL Translator
MC100LVEL92_06	ONSEMI	获取价格	5V Triple PECL Input to LVPECL Output Translator
MC100LVEL92DW	ONSEMI	获取价格	5V Triple PECL Input to LVPECL Output Translator
MC100LVEL92DW	MOTOROLA	获取价格	Triple PECL to LVPECL Translator
MC100LVEL92DWG	ONSEMI	获取价格	5V Triple PECL Input to LVPECL Output Translator

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