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MC100LVELT20_06 PDF预览

MC100LVELT20_06

更新时间: 2024-01-23 11:48:24
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
7页 107K
描述
3.3VLVTTL/LVCMOS to Differential LVPECL Translator

MC100LVELT20_06 数据手册

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MC100LVELT20  
Product Preview  
3.3VꢀLVTTL/LVCMOS to  
Differential LVPECL  
Translator  
http://onsemi.com  
Description  
The MC100LVELT20 is a 3.3 V TTL/CMOS to differential PECL  
translator. Because PECL (Positive ECL) levels are used, only + 3.3 V  
and ground are required. The small outline SOIC8 package and the  
single gate of the MC100LVELT20 makes it ideal for those  
applications where space, performance, and low power are at a  
premium.  
MARKING  
DIAGRAM  
8
8
KVT20  
ALYW  
G
1
The 100 Series contains temperature compensation.  
SO8  
1
D SUFFIX  
CASE 751  
Features  
390 ps Typical Propagation Delay  
Maximum Input Clock Frequency > 0.8 GHz Typical  
A
L
= Assembly Location  
= Wafer Lot  
Operating Range V = 3.0 V to 3.6 V with GND = 0 V  
CC  
Y
W
G
= Year  
= Work Week  
= PbFree Package  
PNP TTL Input for Minimal Loading  
Q Output will Default HIGH with Input Open  
PbFree Packages are Available  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
This document contains information on a product under development. ON Semiconductor  
reserves the right to change or discontinue this product without notice.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 Rev. P3  
MC100LVELT20/D  

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