Datasheet > MC100LVELT23_06

MC100LVELT23_06

更新时间： 2024-01-24 09:39:15

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
8页	138K
描述
3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator

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MC100LVELT23_06 数据手册

MC100LVELT23

3.3 VꢀDual Differential

LVPECL/LVDS to LVTTL

Translator

Description

http://onsemi.com

MARKING

The MC100LVELT23 is a dual differential LVPECL/LVDS to

LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels

are used only +3.3 V and ground are required. The small outline 8-lead

package and the dual gate design of the LVELT23 makes it ideal for

applications which require the translation of a clock and a data signal.

The LVELT23 is available in only the ECL 100K standard. Since

there are no LVPECL outputs or an external V

LVELT23 does not require both ECL standard versions. The LVPECL

inputs are differential. Therefore, the MC100LVELT23 can accept any

DIAGRAMS*

KVT23

ALYW

reference, the

SOIC−8

D SUFFIX

CASE 751

standard differential LVPECL input referenced from a V of +3.3 V.

Features

• 2.0 ns Typical Propagation Delay

• Maximum Frequency > 180 MHz

• Differential LVPECL Inputs

KR23

ALYWG

TSSOP−8

DT SUFFIX

CASE 948R

• PECL Mode Operating Range:V = 3.0 V to 3.8 V

with GND = 0 V

• 24 mA LVTTL Outputs

• Flow Through Pinouts

• Internal Pulldown and Pullup Resistors

• Pb−Free Packages are Available

DFN8

MN SUFFIX

CASE 506AA

= Assembly Location

= Wafer Lot

= Year

W = Work Week

M = Date Code

= Pb−Free Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

Publication Order Number:

December, 2006 − Rev. 14

MC100LVELT23/D

12 3 4 5 6 7 8

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