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MC100LVELT22DG PDF预览

MC100LVELT22DG

更新时间: 2024-11-20 05:30:07
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
7页 80K
描述
3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator

MC100LVELT22DG 数据手册

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MC100LVELT22  
3.3VꢀDual LVTTL/LVCMOS  
to Differential LVPECL  
Translator  
Description  
http://onsemi.com  
MARKING  
The MC100LVELT22 is a dual LVTTL/LVCMOS to differential  
LVPECL translator. Because LVPECL (Low Voltage Positive ECL)  
levels are used, only +3.3 V and ground are required. The small outline  
8-lead package and the low skew, dual gate design of the LVELT22  
makes it ideal for applications which require the translation of a clock  
and a data signal.  
DIAGRAMS*  
8
8
1
KVT22  
ALYW  
G
Features  
SOIC−8  
D SUFFIX  
CASE 751  
350 ps Typical Propagation Delay  
<100 ps Output−to−Output Skew  
Flow Through Pinouts  
1
8
8
The 100 Series Contains Temperature Compensation  
1
KR22  
LVPECL Operating Range: V = 3.0 V to 3.8 V  
CC  
ALYWG  
TSSOP−8  
DT SUFFIX  
CASE 948R  
with GND = 0 V  
G
When Unused TTL Input is left Open, Q Output will Default High  
Pb−Free Packages are Available  
1
DFN8  
MN SUFFIX  
CASE 506AA  
1
4
A
L
Y
= Assembly Location  
= Wafer Lot  
= Year  
W = Work Week  
M = Date Code  
G
= Pb−Free Package  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2007  
1
Publication Order Number:  
March, 2007 − Rev. 5  
MC100LVELT22/D  

MC100LVELT22DG 替代型号

型号 品牌 替代类型 描述 数据表
MC100EPT22DTG ONSEMI

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3.3V Dual LVTTL/LVCMOS to Differential LVPECL to Differential LVPECL
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3.3V Dual LVTTL/LVCMOS to Differential LVPECL to Differential LVPECL

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