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MC100LVELT23MNRG PDF预览

MC100LVELT23MNRG

更新时间: 2024-01-15 21:49:48
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管接口集成电路锁存器
页数 文件大小 规格书
8页 162K
描述
3.3V Dual Differential LVPECL/LVDS to LVTTL Translator

MC100LVELT23MNRG 技术参数

是否无铅: 不含铅生命周期:Active
零件包装代码:DFN包装说明:HVSON, SOLCC8,.08,20
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:1.67
最大延迟:2.5 ns接口集成电路类型:PECL TO TTL TRANSLATOR
JESD-30 代码:S-PDSO-N8长度:2 mm
湿度敏感等级:1位数:1
功能数量:2端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
输出锁存器或寄存器:NONE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:HVSON
封装等效代码:SOLCC8,.08,20封装形状:SQUARE
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
座面最大高度:1 mm子类别:Level Translators
最大供电电压:3.8 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Nickel/Gold/Palladium (Ni/Au/Pd)端子形式:NO LEAD
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:2 mm
Base Number Matches:1

MC100LVELT23MNRG 数据手册

 浏览型号MC100LVELT23MNRG的Datasheet PDF文件第2页浏览型号MC100LVELT23MNRG的Datasheet PDF文件第3页浏览型号MC100LVELT23MNRG的Datasheet PDF文件第4页浏览型号MC100LVELT23MNRG的Datasheet PDF文件第5页浏览型号MC100LVELT23MNRG的Datasheet PDF文件第6页浏览型号MC100LVELT23MNRG的Datasheet PDF文件第7页 
MC100LVELT23  
3.3ꢀVꢁDual Differential  
LVPECL/LVDS to LVTTL  
Translator  
Description  
www.onsemi.com  
The MC100LVELT23 is a dual differential LVPECL/LVDS to  
LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels  
are used only +3.3 V and ground are required. The small outline 8-lead  
package and the dual gate design of the LVELT23 makes it ideal for  
applications which require the translation of a clock and a data signal.  
The LVELT23 is available in only the ECL 100K standard. Since  
there are no LVPECL outputs or an external V  
LVELT23 does not require both ECL standard versions. The LVPECL  
inputs are differential. Therefore, the MC100LVELT23 can accept any  
8
8
1
1
1
SOIC8 NB  
D SUFFIX  
TSSOP8  
DT SUFFIX  
CASE 75107 CASE 948R02  
DFN8  
MN SUFFIX  
CASE 506AA  
reference, the  
BB  
standard differential LVPECL input referenced from a V of +3.3 V.  
CC  
MARKING DIAGRAMS*  
Features  
2.0 ns Typical Propagation Delay  
Maximum Frequency > 180 MHz  
Differential LVPECL Inputs  
8
8
1
KVT23  
ALYW  
G
KR23  
ALYWG  
G
PECL Mode Operating Range:V = 3.0 V to 3.8 V  
1
4
CC  
1
with GND = 0 V  
SOIC8  
TSSOP8  
DFN8  
24 mA LVTTL Outputs  
Flow Through Pinouts  
Internal Pulldown and Pullup Resistors  
These Devices are Pb-Free, Halogen Free and are RoHS Compliant  
A
L
Y
= Assembly Location  
= Wafer Lot  
= Year  
W = Work Week  
M = Date Code  
G
= Pb-Free Package  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
Device  
Package  
Shipping  
MC100LVELT23DG  
SOIC8 NB  
98 Units/Tube  
(Pb-Free)  
MC100LVELT23DR2G SOIC8 NB 2500/Tape & Reel  
(Pb-Free)  
MC100LVELT23DTG  
TSSOP8  
(Pb-Free)  
100 Units/Tube  
2500/Tape & Reel  
1000/Tape & Reel  
MC100LVELT23DTRG TSSOP8  
(Pb-Free)  
MC100LVELT23MNRG  
DFN8  
(Pb-Free)  
†For information on tape and reel specifications, in-  
cluding part orientation and tape sizes, please refer  
to our Tape and Reel Packaging Specifications  
Brochure, BRD8011/D.  
© Semiconductor Components Industries, LLC, 2016  
1
Publication Order Number:  
July, 2016 Rev. 19  
MC100LVELT23/D  

MC100LVELT23MNRG 替代型号

型号 品牌 替代类型 描述 数据表
MC100LVELT23DTG ONSEMI

完全替代

3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator
MC100LVELT23DG ONSEMI

完全替代

3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator

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