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MC100LVEP14_06

更新时间： 2024-01-13 12:31:28
品牌 Logo 应用领域
安森美 - ONSEMI 时钟驱动器
页数 文件大小 规格书
9页 138K
描述
2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock Driver

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MC100LVEP14_06 数据手册

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MC100LVEP14  
2.5V / 3.3Vꢀ1:5 Differential  
ECL/PECL/HSTL Clock Driver  
Description  
The MC100LVEP14 is a low skew 1−to−5 differential driver, designed  
with clock distribution in mind, accepting two clock sources into an input  
multiplexer. The ECL/PECL input signals can be either differential or  
http://onsemi.com  
single−ended (if the V output is used). HSTL inputs can be used when  
BB  
the LVEP14 is operating under PECL conditions.  
The LVEP14 specifically guarantees low output−to−output skew.  
Optimal design, layout, and processing minimize skew within a device and  
from device to device.  
To ensure that the tight skew specification is realized, both sides of  
any differential output need to be terminated identically into 50 W  
even if only one output is being used. If an output pair is unused, both  
outputs may be left open (unterminated) without affecting skew.  
The common enable (EN) is synchronous, outputs are enabled/  
disabled in the LOW state. This avoids a runt clock pulse when the  
device is enabled/disabled as can happen with an asynchronous  
control. The internal flip flop is clocked on the falling edge of the input  
clock; therefore, all associated specification limits are referenced to  
the negative edge of the clock input.  
TSSOP−20  
DT SUFFIX  
CASE 948E  
MARKING DIAGRAM*  
20  
100  
VP14  
The MC100LVEP14, as with most other ECL devices, can be  
ALYWG  
operated from a positive V supply in PECL mode. This allows the  
CC  
G
LVEP14 to be used for high performance clock distribution in +3.3 V  
or +2.5 V systems. Single−ended CLK input pin operation is limited to  
1
a V ≥ 3.0 V in PECL mode, or V ≤ −3.0 V in NECL mode.  
Designers can take advantage of the LVEP14’s performance to  
distribute low skew clocks across the backplane or the board.  
CC  
EE  
A
L
Y
W
G
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
Features  
(Note: Microdot may be in either location)  
• 100 ps Device−to−Device Skew  
• 25 ps Within Device Skew  
*For additional marking information, refer to  
Application Note AND8002/D.  
• 400 ps Typical Propagation Delay  
• Maximum Frequency > 2 GHz Typical  
• The 100 Series Contains Temperature Compensation  
• PECL and HSTL Mode:  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 6 of this data sheet.  
V
CC  
= 2.375 V to 3.8 V with V = 0 V  
EE  
• NECL Mode:  
= 0 V with V = −2.375 V to −3.8 V  
V
CC  
EE  
• LVDS Input Compatible  
• Open Input Default State  
• Pb−Free Packages are Available*  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 − Rev. 11  
MC100LVEP14/D  
1234567...9

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