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MC100LVEP210FAR2 PDF预览

MC100LVEP210FAR2

更新时间： 2024-01-20 04:03:59
品牌 Logo 应用领域
安森美 - ONSEMI 时钟驱动器逻辑集成电路
页数 文件大小 规格书
8页 138K
描述
Low-Voltage 1:5 Dual Diff.LVECL/LVPECL/LVEPECL/HSTL Clock Driver

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中文翻译

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MC100LVEP210FAR2 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：PLASTIC, LQFP-32
针数：32Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.4
其他特性：NECL MODE: VCC = 0V WITH VEE = -2.375V TO -3.8V系列：100LVE
输入调节：DIFFERENTIALJESD-30 代码：S-PQFP-G32
JESD-609代码：e0长度：7 mm
逻辑集成电路类型：LOW SKEW CLOCK DRIVER功能数量：2
反相输出次数：端子数量：32
实输出次数：5最高工作温度：85 °C
最低工作温度：-40 °C输出特性：OPEN-EMITTER
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP32,.35SQ,32封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE峰值回流温度（摄氏度）：240
电源：+-2.375/+-3.8 VProp。Delay @ Nom-Sup：0.49 ns
传播延迟（tpd）：0.43 ns认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.025 ns座面最大高度：1.6 mm
子类别：Clock Drivers最大供电电压 (Vsup)：3.8 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：ECL
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn80Pb20)
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：7 mmBase Number Matches：1

MC100LVEP210FAR2 数据手册

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The MC100LVEP210 is a low skew 1–to–5 dual differential driver,  
designed with clock distribution in mind. The LVECL/LVPECL input  
http://onsemi.com  
signals can be either differential or single–ended if the V  
output is  
BB  
used. The signal is fanned out to 5 identical differential outputs. HSTL  
inputs can be used when the EP210 is operating in LVPECL mode.  
The LVEP210 specifically guarantees low output–to–output skew.  
Optimal design, layout, and processing minimize skew within a device  
and from lot to lot.  
To ensure the tight skew specification is realized, both sides of the  
differential output need to be terminated identically into 50Ω even if  
only one side is being used. When fewer than all ten pairs are used,  
identically terminate all the output pairs on the same package side  
whether used or unused. If no outputs on a single side are used, then  
leave these outputs open (unterminated). This will maintain minimum  
output skew. Failure to do this will result in a 10–20ps loss of skew  
margin (propagation delay) in the output(s) in use.  
32–LEAD TQFP  
FA SUFFIX  
CASE 873A  
MARKING DIAGRAM*  
A
= Assembly Location  
MC100  
LVEP210  
AWLYYWW  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
The MC100LVEP210, as with most other LVECL devices, can be  
operated from a positive V  
supply in LVPECL mode. This allows  
CC  
the LVEP210 to be used for high performance clock distribution in  
+3.3V or +2.5V systems. Single ended input operation is limited to a  
VCC ≥ 3.0V in PECL mode, or VEE ≤ –3.0V in ECL mode.  
Designers can take advantage of the LVEP210’s performance to  
distribute low skew clocks across the backplane or the board. In a  
LVPECL environment, series or Thevenin line terminations are  
typically used as they require no additional power supplies. For more  
information on using PECL, designers should refer to Application  
Note AN1406/D.  
32  
1
*For additional information, see Application Note  
AND8002/D  
ORDERING INFORMATION  
Device  
Package  
Shipping  
• 100ps Part–to–Part Skew  
• 35ps Output–to–Output Skew  
• Differential Design  
MC100LVEP210FA  
TQFP  
250 Units/Tray  
MC100LVEP210FAR2 TQFP  
2000 Tape & Reel  
• V Output  
BB  
• 475ps Typical Propagation Delay  
• High Bandwidth to 1.5GHz Typical  
• LVPECL and HSTL mode: 2.375V to 3.8V V  
with V = 0V  
EE  
CC  
• LVECL mode: 0V V  
with V = –2.375V to –3.8V  
CC  
EE  
• Internal Input Resistors: Pulldown on D, D  
• Pullup and Pulldown on CLK  
• ESD Protection: >2KV HBM, >100V MM  
• Moisture Sensitivity Level 2  
For Additional Information, See Application Note AND8003/D  
• Flammability Rating: UL–94 code V–0 @ 1/8”,  
Oxygen Index 28 to 34  
• Transistor Count = 461 devices  
Semiconductor Components Industries, LLC, 1999  
1
Publication Order Number:  
March, 2000 – Rev. 2  
MC100LVEP210/D  
12345678

中文翻译

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MC100LVEP210FAR2 替代型号

型号 品牌 替代类型 描述 数据表
MC100LVEP210FAG ONSEMI

类似代替

 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver
MC100LVEP210FARG ONSEMI

类似代替

 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver
ICS853210BY IDT

功能相似

 Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM H

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