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MC100LVEP14DTR2

更新时间： 2024-11-17 22:16:11
品牌 Logo 应用领域
安森美 - ONSEMI 时钟驱动器
页数 文件大小 规格书
8页 115K
描述
Low-Voltage 1:5 Differential LVECL/LVPECL/LVEPECL/HSTL Clock Driver

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中文翻译

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MC100LVEP14DTR2 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP20,.25针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.44其他特性：NECL MODE: VCC = 0V WITH VEE = -2.375V TO -3.8V
系列：100LVE输入调节：DIFFERENTIAL MUX
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：6.5 mm逻辑集成电路类型：LOW SKEW CLOCK DRIVER
功能数量：1反相输出次数：
端子数量：20实输出次数：5
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：OPEN-EMITTER封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP20,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：-4.5 V
Prop。Delay @ Nom-Sup：0.525 ns传播延迟（tpd）：0.475 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.025 ns
座面最大高度：1.2 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.8 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：ECL温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：4.4 mm
最小 fmax：2000 MHzBase Number Matches：1

MC100LVEP14DTR2 数据手册

 浏览型号MC100LVEP14DTR2的Datasheet PDF文件第2页浏览型号MC100LVEP14DTR2的Datasheet PDF文件第3页浏览型号MC100LVEP14DTR2的Datasheet PDF文件第4页浏览型号MC100LVEP14DTR2的Datasheet PDF文件第5页浏览型号MC100LVEP14DTR2的Datasheet PDF文件第6页浏览型号MC100LVEP14DTR2的Datasheet PDF文件第7页 
The MC100LVEP14 is a low skew 1–to–5 differential driver, designed  
with clock distribution in mind, accepting two clock sources into an input  
multiplexer. The LVECL/LVPECL input signals can be either differential  
http://onsemi.com  
or single–ended (if the V  
when the LVEP14 is operating under LVPECL conditions.  
output is used). HSTL inputs can be used  
BB  
The LVEP14 specifically guarantees low output–to–output skew.  
Optimal design, layout, and processing minimize skew within a device and  
from lot to lot.  
20  
1
To ensure that the tight skew specification is realized, both sides of  
any differential output need to be terminated identically into 50 even  
if only one side is being used. When fewer than all five pairs are used,  
identically terminate all the output pairs on the same package side  
whether used or unused. If no outputs on a single side are used, then  
leave these outputs open (unterminated). This will maintain minimum  
output skew. Failure to do this will result in a 10–20ps loss of skew  
margin (propagation delay) in the output(s) in use.  
The common enable (EN) is synchronous, outputs are enabled/  
disabled in the LOW state. This avoids a runt clock pulse when the  
device is enabled/disabled as can happen with an asynchronous  
control. The internal flip flop is clocked on the falling edge of the input  
clock, therefore all associated specification limits are referenced to the  
negative edge of the clock input.  
TSSOP–20  
DT SUFFIX  
CASE 948E  
MARKING DIAGRAM*  
VP = LVEP  
100  
A = Assembly Location  
L = Wafer Lot  
Y = Year  
VP14  
ALYW  
W = Work Week  
*For additional information, see Application Note  
AND8002/D  
The MC100LVEP14, as with most other LVECL devices, can be  
operated from a positive V  
supply in LVPECL mode. This allows  
CC  
the LVEP14 to be used for high performance clock distribution in  
+3.3V or +2.5V systems. Single ended input operation is limited to a  
V
CC  
≥ 3.0V in LVPECL mode, or V ≤ –3.0V in LVECL mode.  
EE  
ORDERING INFORMATION  
Designers can take advantage of the LVEP14’s performance to  
distribute low skew clocks across the backplane or the board. For more  
information, refer to Application Note AN1406/D.  
Device  
Package  
Shipping  
MC100LVEP14DT  
TSSOP  
75 Units/Tray  
• 100ps Part–to–Part Skew  
• 25ps Output–to–Output Skew  
• Differential Design  
MC100LVEP14DTR2 TSSOP 2500 Tape & Reel  
• 400ps Typical Propagation Delay  
• High Bandwidth to 1.5 Ghz Typical  
• LVPECL and HSTL mode: +2.375V to +3.8V V  
with V = 0V  
EE  
CC  
• LVECL mode: 0V V  
CC  
with V = –2.375V to –3.8V  
EE  
• 75kΩ Internal Pulldown CLKs, Pull up & Pulldown CLKs  
• ESD Protection: >2KV HBM; >100V MM  
• Moisture Sensitivity Level 2  
For Additional Information, See Application Note AND8003/D  
• Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34  
• Transistor Count = 357 devices  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
May, 2000 – Rev. 1  
MC100LVEP14/D  
12345678

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