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MC100LVEP210_14

更新时间： 2024-11-22 01:12:55
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
9页 109K
描述
2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver

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MC100LVEP210_14 数据手册

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MC100LVEP210  
2.5V / 3.3Vꢀ1:5 Dual  
Differential ECL/PECL/HSTL  
Clock Driver  
Description  
http://onsemi.com  
MARKING  
The MC100LVEP210 is a low skew 1−to−5 dual differential driver,  
designed with clock distribution in mind. The ECL/PECL input  
signals can be either differential or single−ended if the V output is  
BB  
DIAGRAMS*  
used. The signal is fanned out to 5 identical differential outputs. HSTL  
inputs can be used when the EP210 is operating in PECL mode.  
The LVEP210 specifically guarantees low output−to−output skew.  
Optimal design, layout, and processing minimize skew within a device  
and from device to device.  
To ensure the tight skew specification is realized, both sides of the  
differential output need to be terminated identically into 50 W even if  
only one output is being used. If an output pair is unused, both outputs  
may be left open (unterminated) without affecting skew.  
MC100  
LVEP21  
AWLYYWWG  
32−LEAD LQFP  
FA SUFFIX  
CASE 873A  
The MC100LVEP210, as with most other ECL devices, can be  
1
operated from a positive V supply in PECL mode. This allows the  
CC  
MC100  
LVEP210  
AWLYYWWG  
G
LVEP210 to be used for high performance clock distribution in +3.3 V  
or +2.5 V systems. Single−ended CLK input operation is limited to a  
32  
1
V
≥ 3.0 V in PECL mode, or V ≤ −3.0 V in ECL mode.  
QFN32  
MN SUFFIX  
CASE 488AM  
CC  
EE  
Designers can take advantage of the LVEP210’s performance to  
distribute low skew clocks across the backplane or the board. In a  
PECL environment, series or Thevenin line terminations are typically  
used as they require no additional power supplies. For more  
information on using PECL, designers should refer to Application  
Note AN1406/D.  
A
= Assembly Location  
= Wafer Lot  
WL  
YY  
WW  
= Year  
= Work Week  
G or G = Pb−Free Package  
Features  
(Note: Microdot may be in either location)  
• 85 ps Typical Device−to−Device Skew  
• 20 ps Typical Output−to−Output Skew  
*For additional marking information, refer to  
Application Note AND8002/D.  
• V Output  
BB  
• Jitter Less than 1 ps RMS  
• 350 ps Typical Propagation Delay  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
• Maximum Frequency u 3 GHz Typical  
• The 100 Series Contains Temperature Compensation  
• PECL and HSTL Mode Operating Range: V = 2.375 V to 3.8 V  
CC  
with V = 0 V  
EE  
• NECL Mode Operating Range: V = 0 V  
CC  
with V = −2.375 V to −3.8 V  
EE  
• Open Input Default State  
• LVDS Input Compatible  
• Fully Compatible with MC100EP210  
• These are Pb−Free Devices  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
May, 2014 − Rev. 15  
MC100LVEP210/D  
1234567...9

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