MC10ELT22, MC100ELT22
5VĄDual TTL to Differential
PECL Translator
The MC10ELT/100ELT22 is a dual TTL to differential PECL
translator. Because PECL (Positive ECL) levels are used only +5 V
and ground are required. The small outline 8-lead package and the low
skew, dual gate design of the ELT22 makes it ideal for applications
which require the translation of a clock and a data signal.
http://onsemi.com
MARKING
• 1.2 ns Typical Propagation Delay
• <300 ps Typical Output to Output Skew
• PNP TTL Inputs for Minimal Loading
• Flow Through Pinouts
DIAGRAMS*
8
1
8
8
1
HLT22
ALYW
KLT22
ALYW
SO–8
• ESD Protection: >2 KV HBM, >200 V MM
D SUFFIX
CASE 751
1
• Operating Range: V = 4.75 V to 5.25 V with GND= 0 V
CC
• No Internal Input Pulldown Resistors
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
8
8
8
HT22
ALYW
KT22
ALYW
• Moisture Sensitivity Level 1
1
TSSOP–8
DT SUFFIX
CASE 948R
For Additional Information, see Application Note AND8003/D
1
1
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 51 devices
L = Wafer Lot
Y = Year
W = Work Week
H = MC10
K = MC100
A = Assembly Location
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
Q0 1
8
7
V
CC
*For additional information, see Application Note
AND8002/D
Q0
Q1
2
3
D0
D1
ORDERING INFORMATION
PECL
TTL
Device
Package
Shipping
6
5
MC10ELT22D
SO–8
98 Units/Rail
MC10ELT22DR2
MC100ELT22D
MC100ELT22DR2
MC10ELT22DT
SO–8
SO–8
2500 Tape & Reel
98 Units/Rail
Q1
4
GND
SO–8
2500 Tape & Reel
98 Units/Rail
TSSOP–8
MC10ELT22DTR2 TSSOP–8 2500 Tape & Reel
MC100ELT22DT TSSOP–8 98 Units/Rail
PIN DESCRIPTION
FUNCTION
PIN
MC100ELT22DTR2 TSSOP–8 2500 Tape & Reel
Qn, Qn
Dn
PECL Differential Outputs*
TTL Inputs
V
GND
Positive Supply
Ground
CC
* Output state undetermined when inputs are open.
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
October, 2000 – Rev. 4
MC10ELT22/D