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MC100SX1230 PDF预览

MC100SX1230

更新时间： 2024-01-02 17:15:09
品牌 Logo 应用领域
安森美 - ONSEMI 解码器编码器
页数 文件大小 规格书
8页 127K
描述
CMI CODER/DECODER

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中文翻译

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MC100SX1230 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：QCCJ, LDCC28,.5SQReach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.88
JESD-30 代码：S-PQCC-J28JESD-609代码：e0
长度：11.5062 mm功能数量：1
端子数量：28最高工作温度：85 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC28,.5SQ
封装形状：SQUARE封装形式：CHIP CARRIER
电源：-4.2/-5.46 V认证状态：Not Qualified
座面最大高度：4.57 mm子类别：Network Interfaces
标称供电电压：5 V表面贴装：YES
技术：BIPOLAR电信集成电路类型：TELECOM CIRCUIT
温度等级：OTHER端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD宽度：11.5062 mm

MC100SX1230 数据手册

 浏览型号MC100SX1230的Datasheet PDF文件第2页浏览型号MC100SX1230的Datasheet PDF文件第3页浏览型号MC100SX1230的Datasheet PDF文件第4页浏览型号MC100SX1230的Datasheet PDF文件第5页浏览型号MC100SX1230的Datasheet PDF文件第6页浏览型号MC100SX1230的Datasheet PDF文件第7页 
Order this document  
from Logic Marketing  
SEMICONDUCTOR TECHNICAL DATA  
The MC100SX1230 device consists of a Binary to CMI Coder and CMI  
to Binary Decoder with integrated loop back capability. The device is  
designed for CMI (Code Mark Inversion) interfaces in transmission  
applications supporting either 139.26 Mbit/s E4 or 155.52 Mbit/s STM1  
line rates.  
• Binary-to-CMI Coder and CMI-to-Binary Decoder  
• Internal Loop Back Test Capability  
• Supports SDH or PDH Applications  
• Low Power  
CMI CODER/DECODER  
• Fully Differential 100K Compatible I/O  
• V  
Reference Available  
BB  
• 75kΩ Input Pulldown Resistors  
• +5V PECL or –5V ECL Operation  
• 28-Pin Surface Mount PLCC Package  
• Asynchronous Reset  
In normal operation, the coder and decoder operate independently.  
Both the coder and decoder operate from a 2X line rate clock. The device  
incorporates test circuitry to support loop back bypass so either the coder  
input can be routed to the decoder output or the decoder input can be  
routed to the coder output. The part is fabricated using Motorola’s proven  
MOSAIC III advanced bipolar process.  
FN SUFFIX  
PLASTIC PLCC PACKAGE  
CASE 776-02  
The device provides a V  
The V  
BB  
current sink/source capability is limited. Whenever used, the V  
output for accepting single-ended inputs.  
pin should only be used as a bias for the MC100SX1230 as its  
BB  
pin  
BB  
should be bypassed to ground via a 0.01µF capacitor.  
CCLK CCLK QCMI QCMI QBIN QBIN DCLK  
out  
out  
out  
24  
22  
23  
21  
19  
25  
20  
PIN NAMES  
18  
17  
16  
15  
LCMI  
LBIN  
26  
27  
DCLK  
out  
Pins  
Function  
CMI , CMI  
in  
CMI Input to Decoder  
Decoder Clock Input  
V
CC  
in  
DCLK , DCLK  
in  
in  
QBIN, QBIN  
Binary Output From Decoder  
Decoder Clock Output  
V
CC  
V
28  
1
EE  
DCLK , DCLK  
out  
out  
V
CCO  
Pinout: 28-Lead PLCC  
V
EE  
BIN , BIN  
CCLK , CCLK  
in  
QCMI, QCMI  
Binary Input to Coder  
Coder Clock Input  
in  
in  
(Top View)  
in  
CMI Output from Coder  
Coder Clock Output  
DCLK  
in  
2
3
4
14  
13  
12  
V
CCO  
CCLK , CCLK  
out  
out  
DCLK  
in  
N/C  
N/C  
RESET  
LBIN  
Asynchronous Reset  
Control Input for Binary  
Loop Back  
V
BB  
LCMI  
Control Input for CMI  
Loop Back  
5
6
7
8
9
10  
11  
RESET CMI  
in  
CMI  
in  
BIN  
in  
BIN CCLK CCLK  
in in in  
MOSAIC III is a trademark of Motorola, Inc.  
This document contains information on a new product. Specifications and information herein are subject to  
change without notice.  
4/94  
REV 0  
Motorola, Inc. 1994  
12345678

中文翻译

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