是否Rohs认证: | 不符合 | 生命周期: | Obsolete |
零件包装代码: | SOIC | 包装说明: | SOP, |
针数: | 8 | Reach Compliance Code: | not_compliant |
ECCN代码: | EAR99 | HTS代码: | 8542.39.00.01 |
Factory Lead Time: | 1 week | 风险等级: | 5.46 |
Is Samacsys: | N | 其他特性: | CAN ALSO OPERATE WITH -2.375 V TO -3.8 V SUPPLY IN NECL MODE |
差分输出: | YES | 驱动器位数: | 1 |
输入特性: | DIFFERENTIAL | 接口集成电路类型: | LINE TRANSCEIVER |
接口标准: | GENERAL PURPOSE | JESD-30 代码: | R-PDSO-G8 |
JESD-609代码: | e0 | 长度: | 4.9 mm |
功能数量: | 1 | 端子数量: | 8 |
最高工作温度: | 85 °C | 最低工作温度: | -40 °C |
封装主体材料: | PLASTIC/EPOXY | 封装代码: | SOP |
封装形状: | RECTANGULAR | 封装形式: | SMALL OUTLINE |
峰值回流温度(摄氏度): | 240 | 认证状态: | Not Qualified |
最大接收延迟: | 0.32 ns | 接收器位数: | 1 |
座面最大高度: | 1.75 mm | 最大供电电压: | 3.8 V |
最小供电电压: | 2.375 V | 标称供电电压: | 2.5 V |
表面贴装: | YES | 技术: | ECL |
温度等级: | INDUSTRIAL | 端子面层: | Tin/Lead (Sn80Pb20) |
端子形式: | GULL WING | 端子节距: | 1.27 mm |
端子位置: | DUAL | 处于峰值回流温度下的最长时间: | 30 |
最大传输延迟: | 0.32 ns | 宽度: | 3.9 mm |
Base Number Matches: | 1 |
型号 | 品牌 | 替代类型 | 描述 | 数据表 |
MC10LVEP16D | ONSEMI |
完全替代 |
2.5V / 3.3V ECL Differential Receiver/Driver | |
MC100LVEP16DR2 | ONSEMI |
完全替代 |
2.5V / 3.3V ECL Differential Receiver/Driver | |
MC10LVEP16DR2 | ONSEMI |
完全替代 |
2.5V / 3.3V ECL Differential Receiver/Driver |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
MC100LVEP16DG | ONSEMI |
获取价格 |
2.5V / 3.3V ECL Differential Receiver/Driver | |
MC100LVEP16DR2 | ONSEMI |
获取价格 |
2.5V / 3.3V ECL Differential Receiver/Driver | |
MC100LVEP16DR2G | ONSEMI |
获取价格 |
2.5V / 3.3V ECL Differential Receiver/Driver | |
MC100LVEP16DT | ONSEMI |
获取价格 |
2.5V / 3.3V ECL Differential Receiver/Driver | |
MC100LVEP16DTG | ONSEMI |
获取价格 |
2.5V / 3.3V ECL Differential Receiver/Driver | |
MC100LVEP16DTR2 | ONSEMI |
获取价格 |
2.5V / 3.3V ECL Differential Receiver/Driver | |
MC100LVEP16DTR2G | ONSEMI |
获取价格 |
2.5V / 3.3V ECL Differential Receiver/Driver | |
MC100LVEP16MNR4 | ONSEMI |
获取价格 |
2.5V / 3.3V ECL Differential Receiver/Driver | |
MC100LVEP16MNR4G | ONSEMI |
获取价格 |
2.5V / 3.3V ECL Differential Receiver/Driver | |
MC100LVEP17 | ONSEMI |
获取价格 |
Clock Management Design Using Low Skew and Low Jitter Devices |