MC100LVEP14DT

更新时间： 2024-01-23 02:18:50

品牌	Logo	应用领域
安森美 - ONSEMI		时钟驱动器
页数	文件大小	规格书
8页	115K
描述
Low-Voltage 1:5 Differential LVECL/LVPECL/LVEPECL/HSTL Clock Driver

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MC100LVEP14DT 数据手册

The MC100LVEP14 is a low skew 1–to–5 differential driver, designed

with clock distribution in mind, accepting two clock sources into an input

multiplexer. The LVECL/LVPECL input signals can be either differential

http://onsemi.com

or single–ended (if the V

when the LVEP14 is operating under LVPECL conditions.

output is used). HSTL inputs can be used

The LVEP14 specifically guarantees low output–to–output skew.

Optimal design, layout, and processing minimize skew within a device and

from lot to lot.

To ensure that the tight skew specification is realized, both sides of

any differential output need to be terminated identically into 50 even

if only one side is being used. When fewer than all five pairs are used,

identically terminate all the output pairs on the same package side

whether used or unused. If no outputs on a single side are used, then

leave these outputs open (unterminated). This will maintain minimum

output skew. Failure to do this will result in a 10–20ps loss of skew

margin (propagation delay) in the output(s) in use.

The common enable (EN) is synchronous, outputs are enabled/

disabled in the LOW state. This avoids a runt clock pulse when the

device is enabled/disabled as can happen with an asynchronous

control. The internal flip flop is clocked on the falling edge of the input

clock, therefore all associated specification limits are referenced to the

negative edge of the clock input.

TSSOP–20

DT SUFFIX

CASE 948E

MARKING DIAGRAM*

VP = LVEP

100

A = Assembly Location

L = Wafer Lot

Y = Year

VP14

ALYW

W = Work Week

*For additional information, see Application Note

AND8002/D

The MC100LVEP14, as with most other LVECL devices, can be

operated from a positive V

supply in LVPECL mode. This allows

the LVEP14 to be used for high performance clock distribution in

+3.3V or +2.5V systems. Single ended input operation is limited to a

≥ 3.0V in LVPECL mode, or V ≤ –3.0V in LVECL mode.

ORDERING INFORMATION

Designers can take advantage of the LVEP14’s performance to

distribute low skew clocks across the backplane or the board. For more

information, refer to Application Note AN1406/D.

Device

Package

Shipping

MC100LVEP14DT

TSSOP

75 Units/Tray

• 100ps Part–to–Part Skew

• 25ps Output–to–Output Skew

• Differential Design

MC100LVEP14DTR2 TSSOP 2500 Tape & Reel

• 400ps Typical Propagation Delay

• High Bandwidth to 1.5 Ghz Typical

• LVPECL and HSTL mode: +2.375V to +3.8V V

with V = 0V

• LVECL mode: 0V V

with V = –2.375V to –3.8V

• 75kΩ Internal Pulldown CLKs, Pull up & Pulldown CLKs

• ESD Protection: >2KV HBM; >100V MM

• Moisture Sensitivity Level 2

For Additional Information, See Application Note AND8003/D

• Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34

• Transistor Count = 357 devices

Semiconductor Components Industries, LLC, 2000

Publication Order Number:

May, 2000 – Rev. 1

MC100LVEP14/D

12 3 4 5 6 7 8

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MC100LVEP14DT 替代型号

型号	品牌	替代类型	描述	数据表
MC100LVEP14DTG	ONSEMI	类似代替	2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock Driver

与MC100LVEP14DT相关器件

型号	品牌	获取价格	描述	数据表
MC100LVEP14DTG	ONSEMI	获取价格	2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock Driver
MC100LVEP14DTR2	ONSEMI	获取价格	Low-Voltage 1:5 Differential LVECL/LVPECL/LVEPECL/HSTL Clock Driver
MC100LVEP14DTR2G	ONSEMI	获取价格	2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock Driver
MC100LVEP16	ONSEMI	获取价格	2.5V / 3.3V ECL Differential Receiver/Driver
MC100LVEP16D	ONSEMI	获取价格	2.5V / 3.3V ECL Differential Receiver/Driver
MC100LVEP16DG	ONSEMI	获取价格	2.5V / 3.3V ECL Differential Receiver/Driver
MC100LVEP16DR2	ONSEMI	获取价格	2.5V / 3.3V ECL Differential Receiver/Driver
MC100LVEP16DR2G	ONSEMI	获取价格	2.5V / 3.3V ECL Differential Receiver/Driver
MC100LVEP16DT	ONSEMI	获取价格	2.5V / 3.3V ECL Differential Receiver/Driver
MC100LVEP16DTG	ONSEMI	获取价格	2.5V / 3.3V ECL Differential Receiver/Driver

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