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MC100LVEP111

更新时间： 2024-11-23 22:16:11
品牌 Logo 应用领域
安森美 - ONSEMI 时钟驱动器
页数 文件大小 规格书
8页 135K
描述
Low-Voltage 1:10 Differential LVECL/LVPECL/LVEPECL/HSTL Clock Driver

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MC100LVEP111 数据手册

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The MC100LVEP111 is a low skew 1–to–10 differential driver,  
designed with clock distribution in mind, accepting two clock sources into  
an input multiplexer. The LVECL/LVPECL input signals can be either  
http://onsemi.com  
differential or single–ended (if the V  
output is used). HSTL inputs can  
BB  
be used when the LVEP111 is operating under LVPECL conditions.  
The LVEP111 specifically guarantees low output–to–output skew.  
Optimal design, layout, and processing minimize skew within a device and  
from lot to lot.  
To ensure that the tight skew specification is realized, both sides of  
any differential output need to be terminated identically into 50 even  
if only one side is being used. When fewer than all ten pairs are used,  
identically terminate all the output pairs on the same package side  
whether used or unused. If no outputs on a single side are used, then  
leave these outputs open (unterminated). This will maintain minimum  
output skew. Failure to do this will result in a 10–20ps loss of skew  
margin (propagation delay) in the output(s) in use.  
32–LEAD TQFP  
FA SUFFIX  
CASE 873A  
MARKING DIAGRAM*  
A
= Assembly Location  
MC100  
LVEP111  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
The MC100LVEP111, as with most other LVECL devices, can be  
AWLYYWW  
operated from a positive V  
supply in LVPECL mode. This allows  
CC  
the LVEP111 to be used for high performance clock distribution in  
+3.3V or +2.5V systems. Single ended input operation is limited to a  
32  
1
V
CC  
≥ 3.0V in LVPECL mode, or V ≤ –3.0V in LVECL mode.  
EE  
*For additional information, see Application Note  
AND8002/D  
Designers can take advantage of the LVEP111’s performance to  
distribute low skew clocks across the backplane or the board. In a  
PECL environment, series or Thevenin line terminations are typically  
used as they require no additional power supplies. For more  
information on using LVPECL, designers should refer to Application  
Note AN1406/D.  
ORDERING INFORMATION  
Device  
Package  
Shipping  
• 100ps Part–to–Part Skew  
• 25ps Output–to–Output Skew  
• Differential Design  
MC100LVEP111FA  
TQFP  
250 Units/Tray  
MC100LVEP111FAR2 TQFP  
2000 Tape & Reel  
• V Output  
BB  
• 430ps Typical Propagation Delay  
• High Bandwidth to 1.5 Ghz Typical  
• LVPECL and HSTL mode: +2.375V to +3.8V V  
with V = 0V  
EE  
CC  
• LVECL mode: 0V V  
with V = –2.375V to –3.8V  
CC  
EE  
• 75kΩ Internal Input Pulldown Resistors on CLKs, Pull up &  
Pulldown resistors on CLKs  
• ESD Protection: >2KV HBM; >100V MM  
• Moisture Sensitivity Level 2  
For Additional Information, See Application Note AND8003/D  
• Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34  
• Transistor Count = 602 devices  
Semiconductor Components Industries, LLC, 1999  
1
Publication Order Number:  
March, 2000 – Rev. 2  
MC100LVEP111/D  
12345678

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