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MC100LVEP11DR2 PDF预览

MC100LVEP11DR2

更新时间: 2024-11-20 21:54:55
品牌 Logo 应用领域
安森美 - ONSEMI 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
10页 133K
描述
2.5V / 3.3V ECL 1:2 Differential Fanout Buffer

MC100LVEP11DR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP8,.25
针数:8Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.33
Is Samacsys:N其他特性:NECL MODE : VCC = 0V WITH VEE = -2.375V TO -3.8V
系列:100LVE输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:8实输出次数:2
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
电源:+-2.375/+-3.8 VProp。Delay @ Nom-Sup:0.36 ns
传播延迟(tpd):0.31 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.02 ns座面最大高度:1.75 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.8 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn80Pb20)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

MC100LVEP11DR2 数据手册

 浏览型号MC100LVEP11DR2的Datasheet PDF文件第2页浏览型号MC100LVEP11DR2的Datasheet PDF文件第3页浏览型号MC100LVEP11DR2的Datasheet PDF文件第4页浏览型号MC100LVEP11DR2的Datasheet PDF文件第5页浏览型号MC100LVEP11DR2的Datasheet PDF文件第6页浏览型号MC100LVEP11DR2的Datasheet PDF文件第7页 
MC10LVEP11, MC100LVEP11  
2.5V / 3.3VꢀECL 1:2  
Differential Fanout Buffer  
The MC10/100LVEP11 is a differential 1:2 fanout buffer. The  
device is pin and functionally equivalent to the EP11 device. With AC  
performance the same as the EP11 device, the LVEP11 is ideal for  
applications requiring lower voltage. Singleended CLK input  
http://onsemi.com  
MARKING  
operation is limited to a V w 3.0 V in PECL mode, or V  
v
CC  
EE  
3.0 V in NECL mode.  
The 100 Series contains temperature compensation.  
DIAGRAMS*  
240 ps Typical Propagation Delay  
Maximum Frequency > 3.0 GHz Typical  
8
1
8
8
HYP11  
AYWW  
KYP11  
AYWW  
PECL Mode Operating Range: V = 2.375 V to 3.8 V  
1
CC  
with V = 0 V  
EE  
SOIC8  
D SUFFIX  
CASE 751  
1
NECL Mode Operating Range: V = 0 V  
CC  
with V = 2.375 V to 3.8 V  
EE  
Open Input Default State  
Q Output Will Default LOW with Inputs Open or at V  
LVDS Input Compatible  
8
1
8
1
8
EE  
1
HU11  
ALYW  
KU11  
ALYW  
TSSOP8  
DT SUFFIX  
CASE 948R  
H
K
A
L
= MC10  
= MC100  
= Assembly Location  
= Wafer Lot  
Y
W
= Year  
= Work Week  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 8 of this data sheet.  
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
February, 2005 Rev. 7  
MC10LVEP11/D  

MC100LVEP11DR2 替代型号

型号 品牌 替代类型 描述 数据表
MC100LVEP11DTG ONSEMI

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MC100LVEP11DG ONSEMI

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