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MC100LVEP05 PDF预览

MC100LVEP05

更新时间: 2024-09-25 03:20:15
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
9页 105K
描述
2.5V / 3.3V ECL 2-Input Differential AND/NAND

MC100LVEP05 数据手册

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MC100LVEP05  
2.5V / 3.3V ECL 2-Input  
Differential AND/NAND  
Description  
The MC100LVEP05 is a 2-input differential AND/NAND gate.  
The MC100LVEP05 is the low voltage version of the MC100EP05  
and is functionally equivalent to the EL05 and LVEL05 devices. With  
AC performance much faster than the LVEL05 device, the  
MC100LVEP05 is ideal for low voltage applications requiring the  
fastest AC performance available.  
http://onsemi.com  
MARKING DIAGRAMS*  
8
1
The 100 Series contains temperature compensation.  
8
1
KU05  
ALYWG  
Features  
ꢀ220 ps Typical Propagation Delay  
ꢀInput Clock Frequency > 3 GHz  
ꢀ0.2 ps Typical RMS Random Clock Period Jitter  
TSSOP-8  
DT SUFFIX  
CASE 948R  
G
LVPECL Mode Operating Range: V = 2.375 V to 3.6 V  
CC  
with V = 0 V  
EE  
ꢀNECL Mode Operating Range: V = 0 V  
CC  
with V = -2.375 V to -3.6 V  
EE  
1
4
6N MG  
ꢀOpen Input Default State  
ꢀQ Output Will Default LOW with Inputs Open  
ꢀThese are Pb-Free Devices*  
G
DFN8  
MN SUFFIX  
CASE 506AA  
K = MC100  
M = Date Code  
Y
= Year  
W = Work Week  
A
L
= Assembly Location  
= Wafer Lot  
G
= Pb-Free Package  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
*For additional information on our Pb-Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©ꢀ Semiconductor Components Industries, LLC, 2007  
May, 2007 - Rev. 0  
1
Publication Order Number:  
MC100LVEP05/D  

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