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MC100LVEP05DTR2G PDF预览

MC100LVEP05DTR2G

更新时间: 2024-11-24 03:20:15
品牌 Logo 应用领域
安森美 - ONSEMI 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 105K
描述
2.5V / 3.3V ECL 2-Input Differential AND/NAND

MC100LVEP05DTR2G 技术参数

是否无铅: 不含铅生命周期:Active
零件包装代码:SOIC包装说明:TSSOP, TSSOP8,.25
针数:8Reach Compliance Code:compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.28Is Samacsys:N
其他特性:NECL MODE: VCC = 0V WITH VEE = -2.375V TO -3.6V系列:100LVEP
JESD-30 代码:S-PDSO-G8JESD-609代码:e3
长度:3 mm逻辑集成电路类型:AND/NAND GATE
湿度敏感等级:3功能数量:1
输入次数:2端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP8,.25封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:-4.5 V
最大电源电流(ICC):38 mAProp。Delay @ Nom-Sup:0.32 ns
传播延迟(tpd):0.32 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.1 mm
子类别:Gates最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:3 mmBase Number Matches:1

MC100LVEP05DTR2G 数据手册

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MC100LVEP05  
2.5V / 3.3V ECL 2-Input  
Differential AND/NAND  
Description  
The MC100LVEP05 is a 2-input differential AND/NAND gate.  
The MC100LVEP05 is the low voltage version of the MC100EP05  
and is functionally equivalent to the EL05 and LVEL05 devices. With  
AC performance much faster than the LVEL05 device, the  
MC100LVEP05 is ideal for low voltage applications requiring the  
fastest AC performance available.  
http://onsemi.com  
MARKING DIAGRAMS*  
8
1
The 100 Series contains temperature compensation.  
8
1
KU05  
ALYWG  
Features  
ꢀ220 ps Typical Propagation Delay  
ꢀInput Clock Frequency > 3 GHz  
ꢀ0.2 ps Typical RMS Random Clock Period Jitter  
TSSOP-8  
DT SUFFIX  
CASE 948R  
G
LVPECL Mode Operating Range: V = 2.375 V to 3.6 V  
CC  
with V = 0 V  
EE  
ꢀNECL Mode Operating Range: V = 0 V  
CC  
with V = -2.375 V to -3.6 V  
EE  
1
4
6N MG  
ꢀOpen Input Default State  
ꢀQ Output Will Default LOW with Inputs Open  
ꢀThese are Pb-Free Devices*  
G
DFN8  
MN SUFFIX  
CASE 506AA  
K = MC100  
M = Date Code  
Y
= Year  
W = Work Week  
A
L
= Assembly Location  
= Wafer Lot  
G
= Pb-Free Package  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
*For additional information on our Pb-Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©ꢀ Semiconductor Components Industries, LLC, 2007  
May, 2007 - Rev. 0  
1
Publication Order Number:  
MC100LVEP05/D  

MC100LVEP05DTR2G 替代型号

型号 品牌 替代类型 描述 数据表
MC100LVEP05DG ONSEMI

完全替代

2.5V / 3.3V ECL 2-Input Differential AND/NAND
MC100LVEP05DR2G ONSEMI

完全替代

ECL 2-Input Differential AND/NAND Gate, SOIC-8 Narrow Body, 2500-REEL
MC100LVEP05DTG ONSEMI

完全替代

2.5V / 3.3V ECL 2-Input Differential AND/NAND

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