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MC100LVELT23DTR2 PDF预览

MC100LVELT23DTR2

更新时间: 2024-02-14 18:36:59
品牌 Logo 应用领域
安森美 - ONSEMI 锁存器接口集成电路光电二极管
页数 文件大小 规格书
8页 70K
描述
3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator

MC100LVELT23DTR2 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:TSSOP, TSSOP8,.19Reach Compliance Code:compliant
风险等级:5.84JESD-30 代码:R-PDSO-G8
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP8,.19
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源:3.3 V认证状态:Not Qualified
子类别:Level Translators标称供电电压:3.3 V
表面贴装:YES技术:ECL100K
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
Base Number Matches:1

MC100LVELT23DTR2 数据手册

 浏览型号MC100LVELT23DTR2的Datasheet PDF文件第2页浏览型号MC100LVELT23DTR2的Datasheet PDF文件第3页浏览型号MC100LVELT23DTR2的Datasheet PDF文件第4页浏览型号MC100LVELT23DTR2的Datasheet PDF文件第5页浏览型号MC100LVELT23DTR2的Datasheet PDF文件第6页浏览型号MC100LVELT23DTR2的Datasheet PDF文件第7页 
MC100LVELT23  
3.3 VꢀDual Differential  
LVPECL/LVDS to LVTTL  
Translator  
The MC100LVELT23 is a dual differential LVPECL/LVDS to  
LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels  
are used only +3.3 V and ground are required. The small outline 8-lead  
package and the dual gate design of the LVELT23 makes it ideal for  
applications which require the translation of a clock and a data signal.  
The LVELT23 is available in only the ECL 100K standard. Since  
http://onsemi.com  
MARKING  
DIAGRAMS*  
8
there are no LVPECL outputs or an external V  
reference, the  
BB  
KVT23  
ALYW  
SOIC−8  
D SUFFIX  
CASE 751  
LVELT23 does not require both ECL standard versions. The LVPECL  
inputs are differential. Therefore, the MC100LVELT23 can accept any  
8
1
1
8
standard differential LVPECL input referenced from a V of +3.3 V.  
CC  
2.0 ns Typical Propagation Delay  
Maximum Frequency > 180 MHz  
Differential LVPECL Inputs  
TSSOP−8  
DT SUFFIX  
CASE 948R  
KR23  
ALYW  
8
1
1
PECL Mode Operating Range:V = 3.0 V to 3.8 V  
CC  
with GND = 0 V  
A
L
Y
W
= Assembly Location  
= Wafer Lot  
= Year  
24 mA LVTTL Outputs  
Flow Through Pinouts  
Internal Pulldown and Pullup Resistors  
Pb−Free Package is Available  
= Work Week  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
February, 2005 − Rev. 12  
MC100LVELT23/D  

MC100LVELT23DTR2 替代型号

型号 品牌 替代类型 描述 数据表
MC100LVELT23DTG ONSEMI

完全替代

3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator
MC100EPT23DG ONSEMI

完全替代

Dual Differential LVPECL to LVTTL Translator
MC100LVELT23DG ONSEMI

完全替代

3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator

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