Datasheet > MC100LVELT22

MC100LVELT22

更新时间： 2024-02-20 17:07:52

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
3页	61K
描述
Dual LVTTL/LVCMOS to Differential LVPECL Translator

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MC100LVELT22 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC100LVELT22 is a dual LVTTL/LVCMOS to differential LVPECL

translator. Because LVPECL (Low Voltage Positive ECL) levels are used,

only +3.3V and ground are required. The small outline 8-lead SOIC

package and the low skew, dual gate design of the LVELT22 makes it

ideal for applications which require the translation of a clock and a data

signal.

• 350ps Typical Propagation Delay

• <100ps Output–to–Output Skew

• Differential LVPECL Outputs

• Small Outline SOIC Package

• Flow Through Pinouts

D SUFFIX

8–LEAD PLASTIC SOIC PACKAGE

CASE 751-05

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

Q0 1

LVTTL/

LVCMOS

LVPECL

PIN DESCRIPTION

FUNCTION

GND

Diff PECL Outputs

LVTTL/LVCMOS Inputs

+3.3V Supply

Ground

12/96

Motorola, Inc. 1996

REV 0

3–1

12 3

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型号	品牌	获取价格	描述	数据表
MC100LVELT22_07	ONSEMI	获取价格	3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator
MC100LVELT22_16	ONSEMI	获取价格	3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator
MC100LVELT22D	ONSEMI	获取价格	3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator
MC100LVELT22DG	ONSEMI	获取价格	3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator
MC100LVELT22DR2	ONSEMI	获取价格	3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator
MC100LVELT22DR2	MOTOROLA	获取价格	DUAL TTL/CMOS TO PECL TRANSLATOR, COMPLEMENTARY OUTPUT, PDSO8, PLASTIC, SOIC-8
MC100LVELT22DR2G	ONSEMI	获取价格	3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator
MC100LVELT22DT	ONSEMI	获取价格	3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator
MC100LVELT22DTG	ONSEMI	获取价格	3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator
MC100LVELT22DTR2	ONSEMI	获取价格	3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator