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MC100LVEL92 PDF预览

MC100LVEL92

更新时间: 2024-01-04 09:18:20
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
3页 75K
描述
Triple PECL to LVPECL Translator

MC100LVEL92 数据手册

 浏览型号MC100LVEL92的Datasheet PDF文件第2页浏览型号MC100LVEL92的Datasheet PDF文件第3页 
SEMICONDUCTOR TECHNICAL DATA  
The MC100LVEL92 is a triple PECL to LVPECL translator. The device  
receives standard PECL signals and translates them to differential  
LVPECL output signals.  
500ps Propagation Delays  
Fully Differential Design  
20–Lead SOIC Package  
5V and 3.3V Supplies Required  
>1500V ESD  
20  
1
A PECL V  
output is provided for interfacing single ended PECL  
BB  
signals at the inputs. If a single ended PECL input is to be used the PECL  
output should be connected to the D input and the active signal will  
V
DW SUFFIX  
PLASTIC SOIC PACKAGE  
CASE 751D-04  
BB  
drive the D input. When used the PECL V  
should be bypassed to  
is designed to act as a  
BB  
BB  
ground via a 0.01µf capacitor. The PECL V  
switching reference for the MC100LVEL92 under single ended input  
conditions, as a result the pin can only source/sink 0.5mA of current.  
To accomplish the PECL to LVPECL level translation, the  
MC100LVEL92 requires three power rails. The V  
connected to the standard PECL supply, the LVCC supply is to be  
connected to the LVPECL supply, and Ground is connected to the system  
supply is to be  
CC  
ground plane. Both the V  
with a 0.01µf capacitor.  
and LVCC should be bypassed to ground  
CC  
Under open input conditions, the D input will be biased at a V /2  
CC  
voltage level and the D input will be pulled to ground. This condition will  
force the “Q” output low, ensuring stability.  
PIN NAMES  
Pins  
Function  
Dn  
Qn  
PECL Inputs  
LVPECL Outputs  
V
PECL Reference Voltage Output  
BB  
LVCC  
V
CC  
V
CC  
for LVPECL Output  
for PECL Inputs  
V
CC  
GND  
Common Ground Rail  
Logic Diagram and Pinout: 20-Lead SOIC (Top View)  
V
Q0  
19  
Q0 LVCC  
Q1  
16  
Q1  
15  
LVCC Q2  
Q2  
12  
V
CC  
CC  
20  
18  
17  
14  
13  
11  
LVPECL  
LVPECL  
LVPECL  
PECL  
1
PECL  
4
PECL  
7
2
3
5
6
8
9
10  
V
D0  
D0 PECL D1  
D1 PECL D2  
D2  
GND  
CC  
V
V
BB  
BB  
7/97  
Motorola, Inc. 1997  
REV 2  

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