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MC100ES6011EJR2 PDF预览

MC100ES6011EJR2

更新时间: 2024-11-27 14:53:11
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
8页 234K
描述
100E SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, LEAD FREE, TSSOP-8

MC100ES6011EJR2 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SOIC包装说明:LEAD FREE, TSSOP-8
针数:8Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.22
其他特性:ECL MODE: VCC = 0V WITH VEE =-2.375 TO -3.8V系列:100E
输入调节:DIFFERENTIALJESD-30 代码:S-PDSO-G8
JESD-609代码:e3长度:3 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:8实输出次数:2
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP8,.19封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:+-2.375/+-3.8 VProp。Delay @ Nom-Sup:0.36 ns
传播延迟(tpd):0.31 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.02 ns座面最大高度:1.1 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.8 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:3 mmBase Number Matches:1

MC100ES6011EJR2 数据手册

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MC100ES6011  
Rev 5, 08/2005  
Freescale Semiconductor  
Technical Data  
2.5 V/3.3 V ECL 1:2 Differential  
Fanout Buffer  
The MC100ES6011 is a differential 1:2 fanout buffer. The ES6011 is ideal for  
applications requiring lower voltage.  
MC100ES6011  
D SUFFIX  
8-LEAD SOIC PACKAGE  
CASE 751-07  
The 100ES Series contains temperature compensation.  
Features  
270 ps Typical Propagation Delay  
EF SUFFIX  
8-LEAD SOIC PACKAGE  
Pb-FREE PACKAGE  
CASE 751-07  
Maximum Frequency > 3 GHz Typical  
PECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V  
ECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V  
Open Input Default State  
DT SUFFIX  
8-LEAD TSSOP PACKAGE  
CASE 1640-01  
Q Output Will Default LOW with Inputs Open or at VEE  
LVDS Input Compatible  
8-Lead SOIC and TSSOP Pb-Free Packages Available  
EJ SUFFIX  
8-LEAD TSSOP PACKAGE  
Pb-FREE PACKAGE  
CASE 1640-01  
ORDERING INFORMATION  
Device  
Package  
SO-8  
Q0  
Q0  
1
8
VCC  
MC100ES6011D  
MC100ES6011DR2  
MC100ES6011EF  
MC100ES6011EFR2  
MC100ES6011DT  
MC100ES6011DTR2  
MC100ES6011EJ  
MC100ES6011EJR2  
SO-8  
SO-8 (Pb-Free)  
SO-8 (Pb-Free)  
TSSOP-8  
2
7
D
TSSOP-8  
TSSOP-8 (Pb-Free)  
TSSOP-8 (Pb-Free)  
Q1  
Q1  
3
4
6
D
PIN DESCRIPTION  
5
VEE  
Pin  
D(1), D(2)  
Function  
ECL Data Inputs  
Q0, Q0 Q1, Q1  
ECL Data Outputs  
Positive Supply  
Negative Supply  
VCC  
VEE  
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram  
1. Pins will default LOW when left open.  
2. Pins will default to 0.572 VCC/2 when left  
open.  
© Freescale Semiconductor, Inc., 2005. All rights reserved.  

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