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MC100ES6056 PDF预览

MC100ES6056

更新时间: 2024-09-16 11:10:55
品牌 Logo 应用领域
飞思卡尔 - FREESCALE 复用器
页数 文件大小 规格书
8页 251K
描述
2.5 V/3.3 V ECL/PECL/LVDS Dual Differential 2:1 Multiplexer

MC100ES6056 数据手册

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MC100ES6056  
Rev 4, 06/2005  
Freescale Semiconductor  
Technical Data  
2.5 V/3.3 V ECL/PECL/LVDS  
Dual Differential 2:1 Multiplexer  
MC100ES6056  
The MC100ES6056 is a dual, fully differential 2:1 multiplexer. The differential  
data path makes the device ideal for multiplexing low skew clock or other skew  
sensitive signals. Multiple VBB pins are provided.  
The VBB pin, an internally generated voltage supply, is available to this device  
only. For single-ended input conditions, the unused differential input is connected  
to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs.  
When used, decouple VBB and VCC via a 0.01 µF capacitor and limit current  
sourcing or sinking to 0.5 mA. When not used, VBB should be left open.  
The device features both individual and common select inputs to address both  
data path and random logic applications.  
DT SUFFIX  
20-LEAD TSSOP PACKAGE  
CASE 948E-03  
The 100ES Series contains temperature compensation.  
Features  
EJ SUFFIX  
20-LEAD TSSOP PACKAGE  
Pb-FREE PACKAGE  
CASE 948E-03  
360 ps Typical Propagation Delays  
Maximum Frequency > 3 GHz Typical  
PECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V  
ECL Mode Operating Range: VCC = 0 V with VEE = –2.375 V to –3.8 V  
Open Input Default State  
ORDERING INFORMATION  
Separate and Common Select  
Device  
Package  
TSSOP-20  
Q Output Will Default LOW with Inputs Open or at VEE  
VBB Outputs  
MC100ES6056DT  
MC100ES6056DTR2  
MC100ES6056EJ  
MC100ES6056EJR2  
TSSOP-20  
LVDS Input Compatible  
TSSOP-20 (Pb-Free)  
TSSOP-20 (Pb-Free)  
20-Lead Pb-Free Package Available  
V
Q0  
19  
Q0 SEL0 COM_SEL SEL1  
V
Q1  
13  
Q1  
12  
V
EE  
CC  
CC  
20  
18  
17  
16  
15  
14  
11  
1
0
1
0
1
2
3
4
5
6
7
8
9
10  
D0a D0a  
V
D0b  
D0b  
D1a  
D1a  
V
D1b  
D1b  
BB0  
BB1  
Warning: All V and V pins must be externally connected to  
CC  
EE  
Power Supply to guarantee proper operation.  
Figure 1. 20-Lead Pinout (Top View) and Logic Diagram  
© Freescale Semiconductor, Inc., 2005. All rights reserved.  

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