Datasheet > MC100ES6056EJR2

MC100ES6056EJR2

更新时间： 2024-09-16 11:10:55

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		复用器逻辑集成电路光电二极管
页数	文件大小	规格书
8页	251K
描述
2.5 V/3.3 V ECL/PECL/LVDS Dual Differential 2:1 Multiplexer

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MC100ES6056EJR2 数据手册

MC100ES6056

Rev 4, 06/2005

Freescale Semiconductor

Technical Data

2.5 V/3.3 V ECL/PECL/LVDS

Dual Differential 2:1 Multiplexer

MC100ES6056

The MC100ES6056 is a dual, fully differential 2:1 multiplexer. The differential

data path makes the device ideal for multiplexing low skew clock or other skew

sensitive signals. Multiple V_BBpins are provided.

The V_BBpin, an internally generated voltage supply, is available to this device

only. For single-ended input conditions, the unused differential input is connected

to V_BBas a switching reference voltage. V_BBmay also rebias AC coupled inputs.

When used, decouple V_BBand V_CCvia a 0.01 µF capacitor and limit current

sourcing or sinking to 0.5 mA. When not used, V_BBshould be left open.

The device features both individual and common select inputs to address both

data path and random logic applications.

DT SUFFIX

20-LEAD TSSOP PACKAGE

CASE 948E-03

The 100ES Series contains temperature compensation.

Features

EJ SUFFIX

20-LEAD TSSOP PACKAGE

Pb-FREE PACKAGE

CASE 948E-03

•

360 ps Typical Propagation Delays

Maximum Frequency > 3 GHz Typical

PECL Mode Operating Range: V_CC= 2.375 V to 3.8 V with V_EE= 0 V

ECL Mode Operating Range: V_CC= 0 V with V_EE= –2.375 V to –3.8 V

Open Input Default State

ORDERING INFORMATION

Separate and Common Select

Device

Package

TSSOP-20

Q Output Will Default LOW with Inputs Open or at V_EE

V_BBOutputs

MC100ES6056DT

MC100ES6056DTR2

MC100ES6056EJ

MC100ES6056EJR2

TSSOP-20

LVDS Input Compatible

TSSOP-20 (Pb-Free)

20-Lead Pb-Free Package Available

Q0 SEL0 COM_SEL SEL1

D0a D0a

D0b

D1a

D1b

BB0

BB1

Warning: All V and V pins must be externally connected to

Power Supply to guarantee proper operation.

Figure 1. 20-Lead Pinout (Top View) and Logic Diagram

12 3 4 5 6 7 8

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