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MC100ES6111AC PDF预览

MC100ES6111AC

更新时间： 2024-09-16 14:53:11
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
12页 299K
描述
Low Skew Clock Driver, 100E Series, 10 True Output(s), 0 Inverted Output(s), ECL, PQFP32, 7 X 7 MM, 1.4 MM HEIGHT, 0.8 MM PITCH, LESD FREE, LQFP-32

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MC100ES6111AC 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP, QFP32,.35SQ,32针数：32
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.67
其他特性：ECL MODE: VCC = 0V WITH VEE = -2.5V OR -3.3V SUPPLY; ALSO OPERATES AT 3.3V SUPPLY系列：100E
输入调节：DIFFERENTIAL MUXJESD-30 代码：S-PQFP-G32
JESD-609代码：e3长度：7 mm
逻辑集成电路类型：LOW SKEW CLOCK DRIVER湿度敏感等级：3
功能数量：1反相输出次数：
端子数量：32实输出次数：10
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP32,.35SQ,32封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE峰值回流温度（摄氏度）：260
电源：-2.5/-3.3/2.5/3.3 V传播延迟（tpd）：0.53 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.035 ns
座面最大高度：1.6 mm子类别：Clock Drivers
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：ECL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：7 mmBase Number Matches：1

MC100ES6111AC 数据手册

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MC100ES6111  
Rev. 5, 07/2005  
Freescale Semiconductor  
Technical Data  
Low Voltage 2.5/3.3 V Differential  
ECL/PECL/HSTL Fanout Buffer  
MC100ES6111  
The MC100ES6111 is a bipolar monolithic differential clock fanout buffer.  
Designed for most demanding clock distribution systems, the MC100ES6111  
supports various applications that require distribution of precisely aligned  
differential clock signals. Using SiGe:C technology and a fully differential  
architecture, the device offers very low skew outputs and superior digital signal  
characteristics. Target applications for this clock driver is high performance clock  
distribution in computing, networking and telecommunication systems.  
LOW-VOLTAGE 1:10 DIFFERENTIAL  
ECL/PECL/HSTL  
CLOCK FANOUT DRIVER  
Features  
•
•
•
•
•
•
•
•
•
•
•
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1:10 differential clock distribution  
35 ps maximum device skew  
Fully differential architecture from input to all outputs  
SiGe:C technology supports near-zero output skew  
Supports DC to 2.7 GHz operation of clock or data signals  
ECL/PECL compatible differential clock outputs  
ECL/PECL/HSTL compatible differential clock inputs  
Single 3.3 V, –3.3 V, 2.5 V or –2.5 V supply  
Standard 32-lead LQFP package  
FA SUFFIX  
32-LEAD LQFP PACKAGE  
CASE 873A-04  
AC SUFFIX  
32-LEAD LQFP PACKAGE  
Pb-FREE PACKAGE  
CASE 873A-04  
32-lead Pb-free package available  
Industrial temperature range  
Pin and function compatible to the MC100EP111  
Functional Description  
The MC100ES6111 is designed for low skew clock distribution systems and supports clock frequencies up to 2.7 GHz. The  
device accepts two clock sources. The CLKA input can be driven by ECL or PECL compatible signals, the CLKB input accepts  
HSTL compatible signals. The selected input signal is distributed to 10 identical, differential ECL/PECL outputs. If VBB is con-  
nected to the CLKA input and bypassed to GND by a 10 nF capacitor, the MC100ES6111 can be driven by single-ended ECL/  
PECL signals utilizing the VBB bias voltage output.  
In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even  
if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts  
being used on that side should be terminated.  
The MC100ES6111 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the  
MC100ES6111 supports positive (PECL) and negative (ECL) supplies. The MC100ES6111 is pin and function compatible to the  
MC100EP111.  
© Freescale Semiconductor, Inc., 2005. All rights reserved.  
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MC100ES6111AC 替代型号

型号 品牌 替代类型 描述 数据表
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