Datasheet > MC100ES6139EJR2

MC100ES6139EJR2

更新时间： 2024-11-29 21:54:07

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		时钟发生器逻辑集成电路光电二极管驱动
页数	文件大小	规格书
12页	240K
描述
3.3V ECL/PECL/HSTL/LVDS 2/4, 4/6 Clock Generation Chip

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MC100ES6139EJR2 数据手册

MC100ES6139

Rev 3, 06/2005

Freescale Semiconductor

Technical Data

3.3 V ECL/PECL/HSTL/LVDS ÷2/4,

÷4/5/6 Clock Generation Chip

MC100ES6139

The MC100ES6139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed

explicitly for low skew clock generation applications. The internal dividers are

synchronous to each other, therefore, the common output edges are all precisely

aligned. The device can be driven by either a differential or single-ended ECL or,

if positive power supplies are used, LVPECL input signals. In addition, by using

the V_BBoutput, a sinusoidal source can be AC coupled into the device. If a single-

ended input is to be used, the V_BBoutput should be connected to the CLK input

and bypassed to ground via a 0.01 µF capacitor.

DT SUFFIX

20-LEAD TSSOP PACKAGE

CASE 948E-03

The common enable (EN) is synchronous so that the internal dividers will only

be enabled/disabled when the internal clock is already in the LOW state. This

avoids any chance of generating a runt clock pulse on the internal clock when the

device is enabled/disabled as can happen with an asynchronous control. The

internal enable flip-flop is clocked on the falling edge of the input clock, therefore,

all associated specification limits are referenced to the negative edge of the clock

input.

Upon startup, the internal flip-flops will attain a random state; therefore, for

systems which utilize multiple ES6139s, the master reset (MR) input must be

asserted to ensure synchronization. For systems which only use one ES6139,

the MR pin need not be exercised as the internal divider design ensures

synchronization between the ÷2/4 and the ÷4/5/6 outputs of a single device. All

V_CCand V_EEpins must be externally connected to power supply to guarantee

proper operation.

EJ SUFFIX

20-LEAD TSSOP PACKAGE

Pb-FREE PACKAGE

CASE 948E-03

ORDERING INFORMATION

Device

Package

TSSOP-20

MC100ES6139DT

MC100ES6139DTR2

MC100ES6139EJ

MC100ES6139EJR2

TSSOP-20

The 100ES Series contains temperature compensation.

TSSOP-20 (Pb-Free)

Features

•

Maximum Frequency >1.0 GHz Typical

50 ps Output-to-Output Skew

PECL Mode Operating Range: V_CC= 3.135 V to 3.8 V with V_EE= 0 V

ECL Mode Operating Range: V_CC= 0 V with V_EE= –3.135 V to –3.8 V

Open Input Default State

Synchronous Enable/Disable

Master Reset for Synchronization of Multiple Chips

V_BBOutput

LVDS and HSTL Input Compatible

20-Lead Pb-Free Package Available

12 3 4 5 6 7...12

中文翻译

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与MC100ES6139EJR2相关器件

型号	品牌	获取价格	描述	数据表
MC100ES6210	FREESCALE	获取价格	Low Voltage 2.5/3.3 V Differential ECL/PECL/HSTL Fanout Buffer
MC100ES6210AC	NXP	获取价格	100E SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LEAD F
MC100ES6210AC	FREESCALE	获取价格	Low Voltage 2.5/3.3 V Differential ECL/PECL/HSTL Fanout Buffer
MC100ES6210FA	FREESCALE	获取价格	Low Voltage 2.5/3.3 V Differential ECL/PECL/HSTL Fanout Buffer
MC100ES6210FA	NXP	获取价格	100E SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LQFP-3
MC100ES6210FA	IDT	获取价格	Low Skew Clock Driver, 100E Series, 5 True Output(s), 0 Inverted Output(s), ECL, PQFP32, L
MC100ES6210FAR2	NXP	获取价格	100E SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTI
MC100ES6210FAR2	IDT	获取价格	Low Skew Clock Driver, 100E Series, 5 True Output(s), 0 Inverted Output(s), ECL, PQFP32, P
MC100ES6210KLFR2	IDT	获取价格	Clock Driver, ECL100K, PQCC32
MC100ES6220	FREESCALE	获取价格	Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer

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