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MC100ES6222AER2

更新时间： 2024-12-02 05:24:27
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
11页 785K
描述
Low Skew Clock Driver, 100E Series, 15 True Output(s), 0 Inverted Output(s), ECL, PQFP52, LEAD FREE, LQFP-52

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MC100ES6222AER2 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：HLQFP, QFP52,.47SQ针数：52
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.25
其他特性：ECL MODE: VCC = 0V WITH VEE = -2.5V OR -3.3V SUPPLY; ALSO OPERATES AT 3.3V SUPPLY系列：100E
输入调节：DIFFERENTIAL MUXJESD-30 代码：S-PQFP-G52
JESD-609代码：e3长度：10 mm
逻辑集成电路类型：LOW SKEW CLOCK DRIVER最大I（ol）：0.005 A
湿度敏感等级：3功能数量：1
反相输出次数：端子数量：52
实输出次数：15封装主体材料：PLASTIC/EPOXY
封装代码：HLQFP封装等效代码：QFP52,.47SQ
封装形状：SQUARE封装形式：FLATPACK, HEAT SINK/SLUG, LOW PROFILE
峰值回流温度（摄氏度）：260电源：-2.5/-3.3/2.5/3.3 V
Prop。Delay @ Nom-Sup：0.97 ns传播延迟（tpd）：0.97 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.13 ns
座面最大高度：1.7 mm子类别：Clock Drivers
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：ECL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：10 mmBase Number Matches：1

MC100ES6222AER2 数据手册

 浏览型号MC100ES6222AER2的Datasheet PDF文件第2页浏览型号MC100ES6222AER2的Datasheet PDF文件第3页浏览型号MC100ES6222AER2的Datasheet PDF文件第4页浏览型号MC100ES6222AER2的Datasheet PDF文件第5页浏览型号MC100ES6222AER2的Datasheet PDF文件第6页浏览型号MC100ES6222AER2的Datasheet PDF文件第7页 
LOW VOLTAGE, 1:15 DIFFERENTIAL  
MC100ES6222  
ECL/PECL CLOCK DIVIDER AND FANOUT BUFFER  
The MC100ES6222 is a bipolar monolithic differential clock fanout buffer. Designed for  
most demanding clock distribution systems, the MC100ES6222 supports various  
applications that require the distribution of precisely aligned differential clock signals.  
Using SiGe technology and a fully differential architecture, the device offers very low skew  
outputs and superior digital signal characteristics. Target applications for this clock driver  
is high performance clock distribution in computing, networking and telecommunication  
systems.  
LOW-VOLTAGE 1:15 DIFFERENTIAL  
ECL/PECL CLOCK DIVIDER  
AND FANOUT DRIVER  
Features  
•
•
•
•
•
•
•
15 differential ECL/PECL outputs (4 output banks)  
2 selectable differential ECL/PECL inputs  
Selectable ÷1 or ÷2 frequency divider  
130 ps maximum device skew  
Supports DC to 3 GHz input frequency  
Single 3.3 V, –3.3 V, 2.5 V or –2.5 V supply  
TB SUFFIX  
52-LEAD LQFP PACKAGE  
EXPOSED PAD  
Standard 52-lead LQFP package with exposed pad for enhanced thermal  
characteristics  
CASE 1336A-01  
•
•
•
Supports industrial temperature range  
Pin and function compatible to the MC100EP222  
52-lead Pb-free Package Available  
Functional Description  
The MC100ES6222 is designed for low skew clock distribution systems and supports  
clock frequencies up to 3 GHz. The CLK0 and CLK1 inputs can be driven by ECL or PECL  
compatible signals. Each of the four output banks of two, three, four and six differential  
clock output pairs can be independently configured to distribute the input frequency or ÷2  
of the input frequency. The FSELA, FSELB, FSELC, FSELD, and CLK_SEL are  
asychronous control inputs. Any changes of the control inputs require a MR pulse for  
resynchronization of the ÷2 outputs. For the functionality of the MR control input, see  
Figure 5. Functional Diagram.  
AE SUFFIX  
52-LEAD LQFP PACKAGE  
EXPOSED PAD  
Pb-FREE PACKAGE  
CASE 1336A-01  
In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only  
one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on  
that side should be terminated.  
The MC100ES6222 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the MC100ES6222  
supports positive (PECL) and negative (ECL) supplies. The MC100ES6222 is pin and function compatible to the MC100EP222.  
IDT™ / ICS™ ECL/PECL CLOCK DIVIDER AND FANOUT BUFFER  
1
MC100ES6222 REV. 6 SEPTEMBER 28, 2012  
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MC100ES6222AER2 替代型号

型号 品牌 替代类型 描述 数据表
854S202AYILFT IDT

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