Datasheet > MC100ES7111FA

MC100ES7111FA

更新时间： 2024-11-30 21:54:11

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟
页数	文件大小	规格书
8页	130K
描述
LOW VOLTAGE 1:10 DIFFERENTIAL LVDS CLOCK FANOUT BUFFER

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MC100ES7111FA 技术参数

生命周期：	Transferred	包装说明：	LQFP,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.8	系列：	100E
输入调节：	DIFFERENTIAL MUX	JESD-30 代码：	S-PQFP-G32
长度：	7 mm	逻辑集成电路类型：	LOW SKEW CLOCK DRIVER
功能数量：	1	反相输出次数：
端子数量：	32	实输出次数：	10
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.05 ns	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	ECL	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	QUAD
宽度：	7 mm	Base Number Matches：	1

MC100ES7111FA 数据手册

Order Number: MC100ES7111/D

Rev 0, 12/2002

SEMICONDUCTOR TECHNICAL DATA

The Motorola MC100ES7111 is a LVDS differential clock fanout buffer.

Designed for most demanding clock distribution systems, the

MC100ES7111 supports various applications that require the distribution

of precisely aligned differential clock signals. Using SiGe technology and

a fully differential architecture, the device offers very low skew outputs

and superior digital signal characteristics. Target applications for this

clock driver are high performance clock distribution in computing,

networking and telecommunication systems.

LOW–VOLTAGE

1:10 DIFFERENTIAL

LVDS CLOCK

FANOUT DRIVER

Features:

• 1:10 differential clock fanout buffer

• 50 ps maximum device skew

• SiGe technology

• Supports DC to 1000 MHz operation of clock or data signals

FA SUFFIX

32–LEAD LQFP PACKAGE

CASE 873A

• LVDS compatible differential clock outputs

• PECL and HSTL/LVDS compatible differential clock inputs

• 3.3V power supply

• Supports industrial temperature range

• Standard 32 lead LQFP package

Functional Description

The MC100ES7111 is designed for low skew clock distribution systems and supports clock frequencies up to 1000 MHz . The

device accepts two clock sources. The CLK0 input accepts LVDS or HSTL compatible signals and CLK1 accepts PECL

compatible signals. The selected input signal is distributed to 10 identical, differential LVDS compatible outputs.

The output enable control is synchronized internally preventing output runt pulse generation. Outputs are only disabled or

enabled when the outputs are already in logic low state (true outputs logic low, inverted outputs logic high). The internal

synchronizer eliminates the setup and hold time requirements for the external clock enable signal. The device is packaged in a

7x7 mm²32-lead LQFP package.

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

1. AC specifications are design targets and subject to change

Motorola, Inc. 2002

12 3 4 5 6 7 8

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与MC100ES7111FA相关器件

型号	品牌	获取价格	描述	数据表
MC100ES8011PD	IDT	获取价格	Low Skew Clock Driver, 100E Series, 2 True Output(s), 0 Inverted Output(s), ECL, PDSO8, SO
MC100ES8011PDR2	IDT	获取价格	Low Skew Clock Driver, 100E Series, 2 True Output(s), 0 Inverted Output(s), ECL, PDSO8, SO
MC100ES8014	IDT	获取价格	Low Voltage 1:5 Differential LVDS Clock Fanout Buffer
MC100ES8111	MOTOROLA	获取价格	Low Voltage 1:10 Differential HSTL Clock Fanout Buffer
MC100ES8111ACR2	NXP	获取价格	100E SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MC100ES8111ACR2	IDT	获取价格	Low Skew Clock Driver, 100E Series, 10 True Output(s), 0 Inverted Output(s), ECL, PQFP32,
MC100ES8111FA	MOTOROLA	获取价格	Low Skew Clock Driver, 100E Series, 10 True Output(s), 0 Inverted Output(s), ECL, PQFP32,
MC100ES8111FA	IDT	获取价格	Low Skew Clock Driver, 100E Series, 10 True Output(s), 0 Inverted Output(s), ECL, PQFP32,
MC100ES8111FAR2	IDT	获取价格	Low Skew Clock Driver, 100E Series, 10 True Output(s), 0 Inverted Output(s), ECL, PQFP32,
MC100H600	ONSEMI	获取价格	9-Bit TTL/ECL Translator

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