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MC100ES8111FAR2 PDF预览

MC100ES8111FAR2

更新时间: 2024-12-01 19:58:51
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
12页 748K
描述
Low Skew Clock Driver, 100E Series, 10 True Output(s), 0 Inverted Output(s), ECL, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026BBA, LQFP-32

MC100ES8111FAR2 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP, QFP32,.35SQ,32针数:32
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.27
系列:100E输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G32JESD-609代码:e0
长度:7 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:10输出特性:OPEN-EMITTER
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP32,.35SQ,32封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):240
电源:1.5/1.8,3.3 VProp。Delay @ Nom-Sup:1.42 ns
传播延迟(tpd):1.42 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.105 ns座面最大高度:1.6 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:ECL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:7 mm
Base Number Matches:1

MC100ES8111FAR2 数据手册

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MC100ES8111  
Low Voltage, 1:10 Differential  
HSTL Clock Fanout Buffer  
®
DATASHEET  
The MC100ES8111 is a bipolar monolithic differential clock fanout buffer. Designed for most  
demanding clock distribution systems, the MC100ES8111 supports various applications that  
require the distribution of precisely aligned differential clock signals. Using SiGe technology  
and a fully differential architecture, the device offers very low skew outputs and superior digital  
signal characteristics. Target applications for this clock driver are high performance clock  
distribution in computing, networking and telecommunication systems.  
LOW-VOLTAGE 1:10  
DIFFERENTIAL  
HSTL CLOCK  
FANOUT BUFFER  
Features  
1:10 differential clock fanout buffer  
80 ps maximum device skew  
SiGe technology  
Supports DC to 625 MHz operation of clock or data signals  
HSTL compatible differential clock outputs  
PECL and HSTL compatible differential clock inputs  
3.3 V power supply for device core, 1.5 V or 1.8 V HSTL output supply  
Supports industrial temperature range  
Standard 32 lead LQFP package  
FA SUFFIX  
32-LEAD LQFP PACKAGE  
CASE 873A-04  
32-lead Pb-free package available  
Functional Description  
The MC100ES8111 is designed for low skew clock distribution systems and supports clock  
frequencies up to 625 MHz. The device accepts two clock sources. The CLK0 input accepts  
HSTL compatible signals and CLK1 accepts PECL compatible signals. The selected input  
signal is distributed to 10 identical, differential HSTL compatible outputs.  
In order to meet the tight skew specification of the device, both outputs of a differential  
output pair should be terminated, even if only one output is used. In the case where not all 10  
outputs are used, the output pairs on the same package side as the parts being used on that  
side should be terminated.  
The HSTL compatible output levels are generated with an open emitter architecture. This  
minimizes part-to-part and output-to-output skew. The open-emitter outputs require a 50 DC  
termination to GND (0 V). The output supply voltage can be either 1.5 V or 1.8 V, the core  
voltage supply is 3.3 V. The output enable control is synchronized internally preventing output  
runt pulse generation. Outputs are only disabled or enabled when the outputs are already in  
logic low state (true outputs logic low, inverted outputs logic high). The internal synchronizer  
eliminates the setup and hold time requirements for the external clock enable signal. The  
device is packaged in a 7x7 mm2 32-lead LQFP package.  
AC SUFFIX  
32-LEAD LQFP PACKAGE  
Pb-FREE PACKAGE  
CASE 873A-04  
ORDERING INFORMATION  
Device  
Package  
LQFP-32  
MC100ES8111FA  
MC100ES8111FAR2  
MC100ES8111AC  
MC100ES8111ACR2  
LQFP-32  
LQFP-32 (Pb-Free)  
LQFP-32 (Pb-Free)  
MC100ES8111 Revision 4  
1
©2009 Integrated Device Technology, Inc.  

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