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MC100H604FNR2 PDF预览

MC100H604FNR2

更新时间: 2024-11-09 04:59:43
品牌 Logo 应用领域
安森美 - ONSEMI 转换器电平转换器驱动程序和接口锁存器接口集成电路
页数 文件大小 规格书
4页 88K
描述
Registered Hex TTL/ECL Translator

MC100H604FNR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:PLASTIC, LCC-28
针数:28Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.25最大延迟:4 ns
接口集成电路类型:TTL TO ECL TRANSLATORJESD-30 代码:S-PQCC-J28
JESD-609代码:e0长度:11.505 mm
位数:1功能数量:6
端子数量:28最高工作温度:85 °C
最低工作温度:输出特性:OPEN-EMITTER
输出锁存器或寄存器:REGISTER输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC28,.5SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):240
电源:5,-5.2 V认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Level Translators
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:ECL温度等级:OTHER
端子面层:Tin/Lead (Sn80Pb20)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:11.505 mm
Base Number Matches:1

MC100H604FNR2 数据手册

 浏览型号MC100H604FNR2的Datasheet PDF文件第2页浏览型号MC100H604FNR2的Datasheet PDF文件第3页浏览型号MC100H604FNR2的Datasheet PDF文件第4页 
SEMICONDUCTOR TECHNICAL DATA  
The MC10H/100H604 is a 6–bit, registered, dual supply TTL to ECL  
translator. The device features differential ECL outputs as well as a choice  
between either a differential ECL clock input or a TTL clock input. The  
asynchronous master reset control is an ECL level input..  
With its differential ECL outputs and TTL inputs the H604 device is ideally  
suited for the transmit function of a HPPI bus type board–to–board interface  
application. The on chip registers simplify the task of synchronizing the data  
between the two boards.  
The device is available in either ECL standard: the 10H device is  
compatible with MECL 10KH logic levels while the 100H device is  
compatible with 100K logic levels.  
FN SUFFIX  
PLASTIC PACKAGE  
CASE 776–02  
Differential 50ECL Outputs  
Choice Between Differential ECL or TTL Clock Input  
Dual Power Supply  
Multiple Power and Ground Pins to Minimize Noise  
Specified Within–Device Skew  
PIN NAMES  
PIN  
FUNCTION  
TTL Data Inputs  
Differential ECL Clock Input  
TTL Clock Input  
ECL Master Reset Input  
True ECL Outputs  
Inverted ECL Outputs  
D0–D5  
CLK, CLK  
TCLK  
MR  
Q0–Q5  
Q0–Q5  
LOGIC SYMBOL  
1 OF 6 BITS  
V
CCE  
V
CCT  
V
EE  
ECL V  
TTL V  
ECL V  
(0V)  
(+5.0V)  
(–5.2V)  
CC  
CC  
EE  
Q
Q
n
n
D
D
n
Q
TRUTH TABLE  
Dn  
MR  
TCLK/CLK  
Qn+1  
L
H
X
L
L
H
Z
Z
X
L
H
L
CLK  
R
Z = LOW to HIGH Transition  
CLK  
CLK  
TCLK  
Pinout: 28–Lead PLCC (Top View)  
*
D1 D2  
V
D3 D4 D5 V  
CCT CCE  
25  
24  
23  
22  
21  
20  
19  
26  
27  
28  
18  
Q5  
D0  
17  
16  
TCLK  
Q5  
Q4  
Q4  
V
MR  
V
BB  
V
BB  
CLK  
CLK  
MR  
15  
14  
13  
12  
2
3
4
CCE  
Q3  
Q3  
1. When using MECL inputs, TCLK must be tied to ground (0V).  
2. When using only one MECL input, the unused MECL input must be tied  
*
V
CCE  
to V , and TCLK must be tied to ground (0V).  
BB  
5
6
7
8
9
10  
11  
3. When using TCLK, both MECL inputs must be tied to V  
(–5.2V).  
EE  
Q0 Q0  
V
Q1 Q1 Q2 Q2  
EE  
9/96  
REV 1  
Motorola, Inc. 1996  

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