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MC100ES7011HD PDF预览

MC100ES7011HD

更新时间: 2024-12-01 21:15:43
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
4页 84K
描述
100E SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, PLASTIC, SOIC-8

MC100ES7011HD 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.68系列:100E
输入调节:DIFFERENTIALJESD-30 代码:R-PDSO-G8
长度:4.9 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:8实输出次数:2
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.05 ns
座面最大高度:1.75 mm子类别:Clock Driver
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
Base Number Matches:1

MC100ES7011HD 数据手册

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Freescale Semiconductor, Inc.  
TECHNICAL DATA  
Order number: MC100ES7011H  
Rev 0, 05/2004  
Product Preview  
MC100ES7011H  
Low Voltage 1:2 Differential  
HSTL/LVDS-to-LVDS Clock Fanout  
Buffer  
1:2 DIFFERENTIAL HSTL/LVDS TO LVDS  
CLOCK FANOUT DRIVER  
The MC100ES7011H is a low voltage 1:2 Differential HSTL/LVDS to LVDS  
clock fanout buffer. Designed for the most demanding clock distribution  
systems, the MC100ES7011H supports various applications that require the  
distribution of precisely aligned differential clock signals. Using SiGe  
technology and a fully differential architecture, the device offers very low skew  
outputs and superior digital signal characteristics. Target applications for this  
clock driver are in high performance clock distribution in computing, networking  
and telecommunication systems.  
D SUFFIX  
8-LEAD SOIC PACKAGE  
CASE 751-06  
Features  
1:2 differential clock fanout buffer  
50 ps maximum device skew  
SiGe Technology  
Supports DC to 1000 MHz operation  
LVDS compatible differential clock outputs  
HSTL/LVDS compatible differential clock inputs  
3.3V power supply  
ORDERING INFORMATION  
Device  
Package  
SO-8  
Supports industrial temperature range  
Standard 8 lead SOIC package  
MC100ES7011HD  
MC100ES7011HDR2  
SO-8  
PIN DESCRIPTION  
Pin  
D, D  
Function  
1
8
7
VCC  
Q0  
Q0  
Q1  
Q1  
HSTL/LVDS Data Inputs  
LVDS Data Outputs  
Positive Supply  
Qn, Qn  
VCC  
2
D
D
VEE  
Negative Supply  
6
5
3
4
VEE  
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram  
This document contains certain information on a new product.  
Specifications and information herein are subject to change without notice.  
742  
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA  

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