Datasheet > MC100ES6226FAR2

MC100ES6226FAR2

更新时间： 2024-12-01 21:14:03

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		/
页数	文件大小	规格书
12页	126K
描述
Low Skew Clock Driver, 100E Series, 9 True Output(s), 0 Inverted Output(s), ECL, PQFP32, LQFP-32

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MC100ES6226FAR2 数据手册

Order Number: MC100ES6226/D

Rev 1, 12/2001

SEMICONDUCTOR TECHNICAL DATA

The Motorola MC100ES6226 is a bipolar monolithic differential clock

distribution buffer and clock divider. Designed for most demanding clock

distribution systems, the MC100ES6226 supports various applications

that require a large number of outputs to drive precisely aligned clock

signals. Using SiGe technology and a fully differential architecture, the

device offers superior digitial signal characteristics and very low clock

skew error. Target applications for this clock driver are high performance

clock distribution systems for computing, networking and

telecommunication systems.

2.5V/3.3V DIFFERENTIAL

LVPECL 1:9 CLOCK

DISTRIBUTION BUFFER AND

CLOCK DIVIDER

Features:

• Fully differential architecture from input to all outputs

• SiGe technology supports near-zero output skew

• Selectable 1:1 or 1:2 frequency outputs

• LVPECL compatible differential clock inputs and outputs

• LVCMOS compatible control inputs

• Single 3.3V or 2.5V supply

• Max. 35 ps maximum output skew (within output bank)

• Max. 50 ps maximum device skew

FA SUFFIX

32–LEAD LQFP PACKAGE

CASE 873A

• Supports DC operation and up to 3 GHz (typ.) clock signals

• Synchronous output enable eliminating output runt pulse generation

and metastability

• Standard 32 lead LQFP package

• Industrial temperature range

Functional Description

MC100ES6226 is designed for very skew critical differential clock distribution systems and supports clock frequencies from

DC up to 3.0 GHz. Typical applications for the MC100ES6226 are primary clock distribution systems on backplanes of

high-performance computer, networking and telecommunication systems, as well as on-board clocking of OC-3, OC-12 and

OC-48 speed communication systems.

The MC100ES6226 can be operated from a 3.3V or 2.5V positive supply without the requirement of a negative supply line.

Each of the output banks of three differential clock output pairs may be independently configured to distribute the input frequency

or half of the input frequency. The FSEL0 and FSEL1 clock frequency selects are asychronous control inputs. Any changes of the

control inputs require a MR pulse for resynchronization of the ÷2 outputs.

Motorola, Inc. 2001

12 3 4 5 6 7...12

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与MC100ES6226FAR2相关器件

型号	品牌	获取价格	描述	数据表
MC100ES6254	MOTOROLA	获取价格	2.5/3.3V Differential LVPECL 2x2 Clock Switch and Fanout Buffer
MC100ES6254	IDT	获取价格	2.5/3.3V DIFFERENTIAL LVPECL 2x2 CLOCK SWITCH AND FANOUT BUFFER
MC100ES6254AC	IDT	获取价格	2.5/3.3V DIFFERENTIAL LVPECL 2x2 CLOCK SWITCH AND FANOUT BUFFER
MC100ES6254ACR2	IDT	获取价格	2.5/3.3V DIFFERENTIAL LVPECL 2x2 CLOCK SWITCH AND FANOUT BUFFER
MC100ES6254FA	IDT	获取价格	2.5/3.3V DIFFERENTIAL LVPECL 2x2 CLOCK SWITCH AND FANOUT BUFFER
MC100ES6254FAR2	IDT	获取价格	2.5/3.3V DIFFERENTIAL LVPECL 2x2 CLOCK SWITCH AND FANOUT BUFFER
MC100ES7011HD	IDT	获取价格	Low Skew Clock Driver, 100E Series, 2 True Output(s), 0 Inverted Output(s), ECL, PDSO8, SO
MC100ES7011HD	NXP	获取价格	100E SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, PLASTIC
MC100ES7011HDR2	NXP	获取价格	100E SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, PLASTIC
MC100ES7011PD	NXP	获取价格	100E SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, PLASTIC

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