Datasheet > MC100ES6220TB

MC100ES6220TB

更新时间： 2024-11-30 11:10:55

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		逻辑集成电路驱动时钟
页数	文件大小	规格书
12页	292K
描述
Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer

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MC100ES6220TB 数据手册

MC100ES6220

Rev 4, 04/2005

Freescale Semiconductor

Technical Data

Low Voltage Dual 1:10 Differential

ECL/PECL Clock Fanout Buffer

MC100ES6220

The MC100ES6220 is a bipolar monolithic differential clock fanout buffer.

Designed for most demanding clock distribution systems, the MC100ES6220

supports various applications that require the distribution of precisely aligned

differential clock signals. Using SiGe technology and a fully differential

architecture, the device offers very low skew outputs and superior digital signal

characteristics. Target applications for this clock driver are high performance

clock distribution in computing, networking and telecommunication systems.

LOW VOLTAGE DUAL

1:10 DIFFERENTIAL ECL/PECL

CLOCK FANOUT BUFFER

Features

•

Two independent 1:10 differential clock fanout buffers

130 ps maximum device skew

SiGe technology

Supports DC to 1 GHz operation of clock or data signals

ECL/PECL compatible differential clock outputs

ECL/PECL compatible differential clock inputs

Single 3.3 V, –3.3 V, 2.5 V or –2.5 V supply

TB SUFFIX

52-LEAD LQFP PACKAGE

EXPOSED PAD

CASE 1336A-01

Standard 52-lead LQFP package with exposed pad for enhanced thermal

characteristics

•

Supports industrial temperature range

Pin and function compatible to the MC100EP220

52-lead Pb-free Package Available

AE SUFFIX

52-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 1336A-01

Functional Description

The MC100ES6220 is designed for low skew clock distribution systems and

supports clock frequencies up to 1 GHz. The device consists of two independent

clock fanout buffers. The CLKA and CLKB inputs can be driven by ECL or PECL compatible signals. The input signal of each

clock buffer is distributed to 10 identical, differential ECL/PECL outputs. If V_BBis connected to the CLKA or CLKB input and

bypassed to GND by a 10 nF capacitor, the MC100ES6220 can be driven by single-ended ECL/PECL signals utilizing the V_BB

bias voltage output.

In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even

if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts

being used on that side should be terminated.

The MC100ES6220 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the

MC100ES6220 supports positive (PECL) and negative (ECL) supplies. The MC100ES6220 is pin and function compatible to the

MC100EP220.

12 3 4 5 6 7...12

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与MC100ES6220TB相关器件

型号	品牌	获取价格	描述	数据表
MC100ES6220TBR2	NXP	获取价格	100E SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLAST
MC100ES6220TBR2	MOTOROLA	获取价格	100E SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, EXPOS
MC100ES6220TBR2	IDT	获取价格	Low Skew Clock Driver, 100E Series, 10 True Output(s), 0 Inverted Output(s), ECL, PQFP52,
MC100ES6221	FREESCALE	获取价格	Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer
MC100ES6221AE	FREESCALE	获取价格	Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer
MC100ES6221AER2	NXP	获取价格	100E SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, LEAD
MC100ES6221TB	FREESCALE	获取价格	Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer
MC100ES6221TB	MOTOROLA	获取价格	100E SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, EXPOS
MC100ES6221TBR2	MOTOROLA	获取价格	100E SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, EXPOS
MC100ES6222	MOTOROLA	获取价格	Low Voltage 1:15 Differential ECL/PECL Clock Divider and Fanout Buffer

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