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MC100ES6210FAR2 PDF预览

MC100ES6210FAR2

更新时间： 2024-11-30 14:53:11
品牌 Logo 应用领域
恩智浦 - NXP 驱动输出元件逻辑集成电路
页数 文件大小 规格书
8页 132K
描述
100E SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTIC, LQFP-32

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MC100ES6210FAR2 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Transferred零件包装代码：QFP
包装说明：LQFP, QFP32,.35SQ,32针数：32
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.27其他特性：ECL MODE: VCC =0V WITH VEE = -2.5V OR -3.3V SUPPLY; ALSO OPERATES AT 3.3V SUPPLY
系列：100E输入调节：DIFFERENTIAL
JESD-30 代码：S-PQFP-G32JESD-609代码：e0
长度：7 mm逻辑集成电路类型：LOW SKEW CLOCK DRIVER
最大I（ol）：0.005 A湿度敏感等级：2
功能数量：2反相输出次数：
端子数量：32实输出次数：5
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP32,.35SQ,32封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE峰值回流温度（摄氏度）：220
电源：-2.5/-3.3/2.5/3.3 VProp。Delay @ Nom-Sup：0.35 ns
传播延迟（tpd）：0.35 ns认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.03 ns座面最大高度：1.6 mm
子类别：Clock Drivers最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：ECL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.8 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：7 mm
Base Number Matches：1

MC100ES6210FAR2 数据手册

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Freescale Semiconductor, Inc.  
Order Number: MC100ES6210/D  
Rev 1, 03/2002  
SEMICONDUCTOR TECHNICAL DATA  
The Motorola MC100ES6210 is a bipolar monolithic differential clock  
fanout buffer. Designed for most demanding clock distribution systems,  
the MC100ES6210 supports various applications that require to distribute  
precisely aligned differential clock signals. Using SiGe technology and a  
fully differential architecture, the device offers very low clock skew outputs  
and superior digital signal characteristics. Target applications for this  
clock driver is high performance clock distribution in computing,  
networking and telecommunication systems.  
LOW VOLTAGE DUAL  
1:5 DIFFERENTIAL  
PECL/ECL/HSTL  
CLOCK FANOUT BUFFER  
Features:  
• Dual 1:5 differential clock distribution  
• 30 ps maximum device skew  
• Fully differential architecture from input to all outputs  
• SiGe technology supports near-zero output skew  
• Supports DC to 3GHz operation of clock or data signals  
• ECL/PECL compatible differential clock outputs  
• ECL/PECL compatible differential clock inputs  
• Single 3.3V, -3.3V, 2.5V or -2.5V supply  
• Standard 32 lead LQFP package  
FA SUFFIX  
32–LEAD LQFP PACKAGE  
CASE 873A  
• Industrial temperature range  
• Pin and function compatible to the MC100EP210  
Functional Description  
The MC100ES6210 is designed for low skew clock distribution  
systems and supports clock frequencies up to 3 GHz. The device  
consists of two independent 1:5 clock fanout buffers. The input signal of  
each fanout buffer is distributed to five identical, differential ECL/PECL  
outputs. Both CLKA and CLKB inputs can be driven by ECL/PECL  
compatible signals.  
If VBB is connected to the CLKA or CLKB input and bypassed to GND by a 10 nF capacitor, the MC100ES6210 can be driven  
by single-ended ECL/PECL signals utilizing the VBB bias voltage output.  
In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if  
only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts  
being used on that side should be terminated.  
The MC100ES6210 can be operated from a single 3.3V or 2.5V supply. As most other ECL compatible devices, the  
MC100ES6210 supports positive (PECL) and negative (ECL) supplies. The is function and pin compatible to the MC100EP210.  
For More Information On This Product,  
Motorola, Inc. 2002  
Go to: www.freescale.com  
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