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MC100ES6130DT PDF预览

MC100ES6130DT

更新时间: 2024-11-30 20:55:07
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恩智浦 - NXP 驱动光电二极管逻辑集成电路
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MC100ES6130DT 数据手册

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Document Number: MC100ES6130  
Rev 2, 09/2005  
Freescale Semiconductor  
Technical Data  
2.5/3.3 V 1:4 PECL Clock Driver  
with 2:1 Input MUX  
MC100ES6130  
The MC100ES6130 is a 2.5 GHz differential PECL 1:4 fanout buffer. The  
ES6130 offers a wide operating range of 2.5 V and 3.3 V and also features a 2:1  
input MUX which is ideal for redundant clock switchover applications. This device  
also includes a synchronous enable pin that forces the outputs into a fixed logic  
state. Enable or disable state is initiated only after the outputs are in a LOW state  
to eliminate the possibility of a runt clock pulse.  
DT SUFFIX  
16-LEAD TSSOP PACKAGE  
CASE 948F-01  
Features  
2 GHz maximum output frequency  
25 ps maximum output-to-output skew  
150 ps part-to-part skew  
350 ps typical propagation delay  
2:1 differential MUX input  
EJ SUFFIX  
16-LEAD TSSOP PACKAGE  
Pb-FREE PACKAGE  
CASE 948F-01  
2.5 / 3.3 V operating range  
LVPECL and HSTL input compatible  
16-lead TSSOP package  
Temperature range –40°C to +85°C  
16-lead Pb-free package available  
ORDERING INFORMATION  
Device  
Package  
TSSOP-16  
MC100ES6130DT  
MC100ES6130DTR2  
MC100ES6130EJ  
MC100ES6130EJR2  
TSSOP-16  
TSSOP-16 (Pb-Free)  
TSSOP-16 (Pb-Free)  
VCC  
EN  
Q0  
Q0  
1
2
3
4
5
16  
15  
14  
Q
D
IN1  
Q1  
Q1  
Q2  
Q2  
13 IN1  
12  
11  
10  
9
IN0  
IN0  
6
7
8
IN_SEL  
VEE  
Q3  
Q3  
Figure 1. 16-Lead Pinout (Top View) and Logic Diagram  
© Freescale Semiconductor, Inc., 2005. All rights reserved.  

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