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MC100ES60T22DR2 PDF预览

MC100ES60T22DR2

更新时间: 2024-11-09 05:10:27
品牌 Logo 应用领域
飞思卡尔 - FREESCALE 锁存器接口集成电路光电二极管
页数 文件大小 规格书
8页 94K
描述
3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Translator

MC100ES60T22DR2 数据手册

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MC100ES60T22  
Rev 2, 2/2005  
Freescale Semiconductor  
Technical Data  
3.3 V Dual LVTTL/LVCMOS to  
Differential LVPECL Translator  
MC100ES60T22  
The MC100ES60T22 is a low skew dual LVTTL/LVCMOS to differential  
LVPECL translator. The low voltage PECL levels, small package, and dual gate  
design are ideal for clock translation applications.  
Features  
280 ps typical propagation delay  
100 ps max output-to-output skew  
D SUFFIX  
8-LEAD SOIC PACKAGE  
CASE 751-06  
LVPECL operating range: VCC = 3.135 V to 3.8 V  
8-lead SOIC and 8-lead TSSOP packages  
Ambient temperature range –40°C to +85°C  
DT SUFFIX  
8-LEAD TSSOP PACKAGE  
CASE 1640-01  
ORDERING INFORMATION  
Q0  
Q0  
1
2
8
7
VCC  
Device  
Package  
SOIC-8  
MC100ES60T22D  
MC100ES60T22DR2  
MC100ES60T22DT  
MC100ES60T22DTR2  
SOIC-8  
D0  
TSSOP-8  
TSSOP-8  
LVPECL  
LVTTL/LVCMOS  
PIN DESCRIPTION  
Q1  
Q1  
3
4
6
5
D1  
Pin  
D0, D1  
Function  
LVTTL/LVCMOS Inputs  
LVPECL Differential Outputs  
Positive Supply  
Qn, Qn  
VCC  
GND  
GND  
Negative Supply  
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram  
© Freescale Semiconductor, Inc., 2005. All rights reserved.  

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