5秒后页面跳转
MC100ES6056 PDF预览

MC100ES6056

更新时间: 2024-11-06 05:10:27
品牌 Logo 应用领域
艾迪悌 - IDT 复用器
页数 文件大小 规格书
9页 1111K
描述
2.5V, 3.3V ECL/LVPECL/LVDS DUAL DIFFERENTIAL 2:1 MULTIPLEXER

MC100ES6056 数据手册

 浏览型号MC100ES6056的Datasheet PDF文件第2页浏览型号MC100ES6056的Datasheet PDF文件第3页浏览型号MC100ES6056的Datasheet PDF文件第4页浏览型号MC100ES6056的Datasheet PDF文件第5页浏览型号MC100ES6056的Datasheet PDF文件第6页浏览型号MC100ES6056的Datasheet PDF文件第7页 
2.5V, 3.3V ECL/LVPECL/LVDS DUAL  
DIFFERENTIAL 2:1 MULTIPLEXER  
MC100ES6056  
The MC100ES6056 is a dual, fully differential 2:1 multiplexer. The differential data path  
makes the device ideal for multiplexing low skew clock or other skew sensitive signals.  
Multiple VBB pins are provided.  
DT SUFFIX  
The VBB pin, an internally generated voltage supply, is available to this device only. For  
single-ended input conditions, the unused differential input is connected to VBB as a  
switching reference voltage. VBB may also rebias AC coupled inputs. When used,  
decouple VBB and VCC via a 0.01 µF capacitor and limit current sourcing or sinking to 0.5  
mA. When not used, VBB should be left open.  
20-LEAD TSSOP PACKAGE  
CASE 948E-03  
The device features both individual and common select inputs to address both data  
path and random logic applications.  
EJ SUFFIX  
20-LEAD TSSOP PACKAGE  
Pb-FREE PACKAGE  
CASE 948E-03  
The 100ES Series contains temperature compensation.  
Features  
360 ps Typical Propagation Delays  
Maximum Frequency > 3 GHz Typical  
PECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V  
ECL Mode Operating Range: VCC = 0 V with VEE = –2.375 V to –3.8 V  
Open Input Default State  
Separate and Common Select  
Q Output Will Default LOW with Inputs Open or at VEE  
VBB Outputs  
EG SUFFIX  
20-LEAD SOIC PACKAGE  
Pb-FREE PACKAGE  
CASE 751D-07  
ORDERING INFORMATION  
LVDS Input Compatible  
20-Lead Pb-Free Package Available  
Device  
Package  
TSSOP-20  
MC100ES6056DT  
MC100ES6056DTR2  
MC100ES6056EJ  
MC100ES6056EJR2  
TSSOP-20  
TSSOP-20 (Pb-Free)  
TSSOP-20 (Pb-Free)  
MC100ES6056EG  
MC100ES6056EGR2  
SOIC-20 (Pb-Free)  
SOIC-20 (Pb-Free)  
VCC  
20  
Q0  
19  
Q0 SEL0COM_SEL SEL1 VCC  
Q1  
13  
Q1  
12  
VEE  
11  
18  
17  
16  
15  
14  
1
0
1
0
1
2
3
4
5
6
7
8
9
10  
D0a D0a VBB0 D0b  
D0b  
D1a  
D1a  
VBB1 D1b  
D1b  
Warning: All VCC and VEE pins must be externally connected to  
Power Supply to guarantee proper operation.  
Figure 1. 20-Lead Pinout (Top View) and Logic Diagram  
IDT™ / ICS™ 2:1 MULTIPLEXER  
1
MC100ES6056 REV. 5 JULY 16, 2007  

与MC100ES6056相关器件

型号 品牌 获取价格 描述 数据表
MC100ES6056DT FREESCALE

获取价格

2.5 V/3.3 V ECL/PECL/LVDS Dual Differential 2:1 Multiplexer
MC100ES6056DT IDT

获取价格

2.5V, 3.3V ECL/LVPECL/LVDS DUAL DIFFERENTIAL 2:1 MULTIPLEXER
MC100ES6056DT MOTOROLA

获取价格

100E SERIES, DUAL 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO20, TSSOP-20
MC100ES6056DTR2 IDT

获取价格

2.5V, 3.3V ECL/LVPECL/LVDS DUAL DIFFERENTIAL 2:1 MULTIPLEXER
MC100ES6056DTR2 FREESCALE

获取价格

2.5 V/3.3 V ECL/PECL/LVDS Dual Differential 2:1 Multiplexer
MC100ES6056DTR2 MOTOROLA

获取价格

100E SERIES, DUAL 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO20, TSSOP-20
MC100ES6056DW MOTOROLA

获取价格

100E SERIES, DUAL 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO20, SOIC-20
MC100ES6056EG IDT

获取价格

2.5V, 3.3V ECL/LVPECL/LVDS DUAL DIFFERENTIAL 2:1 MULTIPLEXER
MC100ES6056EGR2 IDT

获取价格

2.5V, 3.3V ECL/LVPECL/LVDS DUAL DIFFERENTIAL 2:1 MULTIPLEXER
MC100ES6056EJ IDT

获取价格

2.5V, 3.3V ECL/LVPECL/LVDS DUAL DIFFERENTIAL 2:1 MULTIPLEXER