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MC100ES6017EG

更新时间: 2024-11-06 11:10:55
品牌 Logo 应用领域
飞思卡尔 - FREESCALE 接口集成电路光电二极管
页数 文件大小 规格书
6页 214K
描述
3.3V ECL/PECL Quad Differential Receiver

MC100ES6017EG 数据手册

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Document Number: MC100ES6017  
Rev 2, 09/2005  
Freescale Semiconductor  
Technical Data  
3.3 V ECL/PECL Quad Differential  
Receiver  
MC100ES6017  
The MC100ES6017 is a 3.3 V ECL/PECL quad differential receiver. Under  
open input conditions, the D input will be biased at VCC/2 and the D input will be  
pulled down to VEE. This operation will force the Q output LOW and ensure  
stability.  
For single-ended input conditions, the unused differential input is connected  
to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs.  
When used, decouple VBB and VCC via a 0.01 µF capacitor and limit current  
sourcing or sinking to 0.5 mA. When not used, VBB should be left open.  
ECL/PECL QUAD  
DIFFERENTIAL RECEIVER  
Features  
High bandwidth output transitions  
LVPECL operating range: VCC = 3.0 V to 3.6 V  
Internal input pulldown resistors on D inputs, pullup and pulldown resistors on  
D inputs  
20 lead SOIC package  
DW SUFFIX  
20-LEAD SOIC PACKAGE  
CASE 751D-07  
Ambient temperature range -40°C to +85°C  
20-lead Pb-free package available  
VCC  
20  
Q0  
19  
Q0  
18  
Q1 Q1  
Q2 Q2  
Q3  
13  
Q3 VEE  
11  
17  
16  
15  
14  
12  
EG SUFFIX  
20-LEAD SOIC PACKAGE  
Pb-FREE PACKAGE  
CASE 751D-07  
ORDERING INFORMATION  
Device  
Package  
SO-20  
MC100ES6017DW  
MC100ES6017DWR2  
MC100ES6017EG  
MC100ES6017EGR2  
3
5
9
10  
1
2
6
7
8
4
SO-20  
VCC  
D0  
D0  
D1  
D1  
D2  
D2  
D3  
D3 VBB  
SO-20 (Pb-Free)  
SO-20 (Pb-Free)  
Figure 1. 20-Lead Pinout (Top View) and Logic Diagram  
PIN DESCRIPTION  
Pin  
Dn, Dn  
Qn, Qn  
VBB  
Function  
ECL Differential Data Inputs  
ECL Differential Data Outputs  
Reference Voltage Output  
Positive Supply  
VCC  
VEE  
Negative Supply  
© Freescale Semiconductor, Inc., 2005. All rights reserved.  

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